Electronic device having time-interleaved circuits

Description

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No. 63/653,238, filed on May 30, 2024. The content of the application is incorporated herein by reference.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The disclosure relates to an electronic device, and more particularly, to an electronic device comprising time-interleaved circuits.

2. Description of the Prior Art

As the spacing of electronic circuits becomes increasingly smaller and the circuits become more complex, more signal transmission lines are required internally. How to effectively utilize the limited layout space of electronic circuits has become a significant challenge in this field.

SUMMARY OF THE DISCLOSURE

According to some embodiments, the disclosure provides an electronic device comprising a data line, a first scan line, a second scan line, a first electronic unit, a second electronic unit, a first circuit unit, and a second circuit unit. The first circuit unit is used to drive the first electronic unit and includes a first time-interleaved circuit. The second circuit unit is adjacent to the first circuit unit and is used to drive the second electronic unit, and includes a second time-interleaved circuit. The data line is coupled to the first circuit unit and the second circuit unit, the first scan line is coupled to the first time-interleaved circuit, and the second scan line is coupled to the second time-interleaved circuit.

These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of an electronic device according to one embodiment of the disclosure.

FIG. 2 is a partial circuit diagram of the electronic device in FIG. 1.

FIG. 3 is a signal timing diagram of the electronic device in FIG. 1.

FIG. 4 is a partial circuit diagram of an electronic device according to another embodiment of the disclosure.

FIG. 5 is a signal timing diagram of the electronic device in FIG. 4.

FIG. 6 is a partial circuit diagram of an electronic device according to another embodiment of the disclosure.

FIG. 7 is a signal timing diagram of the electronic device in FIG. 6.

FIG. 8 is a partial circuit diagram of an electronic device according to another embodiment of the disclosure.

DETAILED DESCRIPTION

For a better understanding of the present disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings. It should be noted that for purposes of clarity and ease of understanding, the drawings may not be drawn to scale, and only a portion of the electronic device is shown in some of the figures. Moreover, the number and arrangement of elements in the figures are exemplary and not intended to be limiting.

As used throughout this specification and the appended claims, certain terms may be used to describe particular features. It will be understood by one of ordinary skill in the art that equivalent components may be referred to by different names in the industry. It is not the intent here to distinguish between those components that are functionally equivalent but that may be described by different names.

As used herein, the terms “including,” “comprising,” or “having” are to be construed as being open-ended terms and mean “including, but not limited to.” Accordingly, when the specification describes a device, method, process, or system as “comprising,” “including,” or “having” a list of elements, those elements are not to be construed as being exclusive or exhaustive of the elements, components, steps, or operations that can be included in such a device, method, process, or system.

The directional terminology used herein, such as “upper,” “lower,” “front,” “back,” “left,” and “right,” is intended to be relative for purposes of description and not as a limitation. The drawings illustrate generally the features of particular embodiments of the present disclosure. However, the drawings are not intended to define or limit the scope or nature of the disclosure. For example, for purposes of clarity, the relative sizes, thicknesses, and positions of various layers, regions, and/or structures may be exaggerated or minimized.

When a component (e.g., a layer or region) is referred to as being “on” another component, it may be directly on the other component, or there may be intervening components therebetween. On the other hand, when a component is referred to as being “directly on” another component, there are no intervening components therebetween. Additionally, when one component is referred to as being “on” another component, the two components have a vertical relationship, and the component may be above or below the other component, depending on the orientation of the device.

It should be understood that when a component or layer is referred to as being “connected to” another component or layer, it may be directly connected to the other component or layer, or there may be intervening components or layers therebetween. When a component is referred to as being “directly connected to” another component or layer, there are no intervening components or layers therebetween. Furthermore, when a component is referred to as being “coupled to” another component (or variations thereof), it may be electrically connected directly to the other component, or it may be indirectly connected (e.g., indirectly electrically connected) to the other component through one or more intervening components.

In the present disclosure, when a component is “disconnected” from another component, an electrical signal cannot flow between the two components at the specified time.

The terms “approximately” or “about” are generally interpreted as being within plus or minus 10% of a given value, or may be interpreted as being within plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1%, or plus or minus 0.5% of a given value.

The use of ordinal terms such as “first,” “second,” etc., to modify an element in the specification and claims is intended solely for the purpose of distinguishing one element having that identifier from another element having the same identifier. The use of such ordinal terms does not imply any chronological order or manufacturing sequence. For example, a first element in the specification may be a second element in a claim.

It should be understood that the various embodiments may be combined to provide further embodiments. That is, the features presented in one embodiment may be included in or substituted for the features presented in other embodiments without departing from the scope of the disclosure.

In the present disclosure, the electronic device may include, but is not limited to, a display device, a light emitting device, an antenna device, a sensing device, a medical device, a splicing device, or any combination thereof. The display device may be a non-emissive display or an emissive display depending on the requirements, and may be a color display or a monochrome display depending on the requirements. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device may be a device for sensing capacitance, light, heat, or ultrasound. The medical device may be a medical testing device. The splicing device may be a display splicing device or an antenna splicing device, but is not limited thereto. The electronic device may include electronic components, which may include passive components and active components such as capacitors, resistors, inductors, diodes, transistors, dies, or chips. The diodes may be dies or chips and may include light emitting diodes (LEDs), photodiodes, or varactors, but are not limited thereto. The LEDS may include, but are not limited to, organic light emitting diodes (OLEDs), mini-LEDs, micro-LEDs, or quantum dot LEDs. The transistors may include, but are not limited to, top-gate thin-film transistors, bottom-gate thin-film transistors, or dual-gate thin-film transistors. The electronic device may also include, but is not limited to, fluorescent materials, phosphor materials, quantum dot (QD) materials, or other suitable materials. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, and the like to support the devices and components in the electronic device.

It should be understood that the features of the various embodiments described herein may be substituted for, rearranged, or combined with each other to form other embodiments without departing from the spirit and scope of the present disclosure.

Referring to FIG. 1, FIG. 1 is a functional block diagram of an electronic device 10A according to one embodiment of the present disclosure. The electronic device 10A comprises a data line 200, a scan line 210A, a scan line 210B, an electronic unit 150A, an electronic unit 150B, a circuit unit 100A, and a circuit unit 100B. The circuit unit 100A is used to drive the electronic unit 150A and comprises a time-interleaved circuit 110A. The circuit unit 100B is arranged in proximity to the circuit unit 100A for driving the electronic unit 150B, and comprises a time-interleaved circuit 110B. The data line 200 is coupled to the circuit unit 100A and the circuit unit 100B, the scan line 210A is coupled to the time-interleaved circuit 110A, and the scan line 210B is coupled to the time-interleaved circuit 110B.

Referring to FIG. 2, FIG. 2 is a partial circuit diagram of the electronic device 10A 1 in FIG. 1. In addition to the time-interleaved circuit 110A, the circuit unit 100A further comprises a driving circuit 120A; and in addition to the time-interleaved circuit 110B, the circuit unit 100B further comprises a driving circuit 120B. At least one of the time-interleaved circuits 110A and 110B comprises a capacitor C. In the embodiment, each of the time-interleaved circuits 110A and 110B comprises a capacitor C. A first end of each capacitor C is coupled to at least two switches T1 and T2, and each switch T1 or T2 comprises at least one transistor, while a second end of each capacitor C is coupled to a system voltage terminal ARVSS. The voltage of the system voltage terminal ARVSS may be, but is not limited to, a ground voltage. In the embodiment, each of the switches T1 and T2 comprises two series-connected P-type transistors, but the present disclosure is not limited thereto. For example, each of the switches T1 and/or T2 may comprise only a single transistor, or the transistors of the switches T1 and/or T2 may be N-type transistors. In the embodiment, the control end (i.e., the gate of the two transistors) of the switch T1 of the time-interleaved circuit 110A receives a scan signal SN[n], a first end of the switch T1 of the time-interleaved circuit 110A is coupled to the scan line 210A to receive a clock signal Sw[1], and a second end of the switch T1 of the time-interleaved circuit 110A outputs a switching signal SN[n_1]. The control end (i.e., the gate of the two transistors) of the switch T2 of the time-interleaved circuit 110A receives a reset signal RST[n], a first end of the switch T2 of the time-interleaved circuit 110A receives a scan signal SN[n], and a second end of the switch T2 of the time-interleaved circuit 110A is coupled to the first end of the capacitor C and the second end of the switch T1 of the time-interleaved circuit 110A. The reset signal RST[n] is used to reset the voltage of the circuit units 100A and 100B. In the embodiment, the circuit structure of the time-interleaved circuit 110B is the same as that of the time-interleaved circuit 110A, except that a first end of the switch T1 of the time-interleaved circuit 110B is coupled to the scan line 210B to receive a clock signal Sw[2], and a second end of the switch T1 of the time-interleaved circuit 110B outputs a switching signal SN[n 2].

The driving circuit 120A comprises a switch T4, a switch T5, and a sub-circuit 160A. In the embodiment, both switches T4 and T5 are P-type transistors. The gate of switch T4 is coupled to the second end of switch T1 to receive a switching signal SN[n_1], the first end of switch T4 is coupled to the data line 200, and the second end of switch T4 is coupled to the sub-circuit 160A. The sub-circuit 160A may comprise a capacitor for storing data transmitted from the data line 200 when the switch T4 is turned on. The gate of switch T5 receives an enable signal EM[n], the first end of switch T5 is coupled to the sub-circuit 160A, and the second end of switch T5 is coupled to the electronic unit 150A. When the switching signal SN[n_1] is low, the switch T4 is turned on; when the switching signal SN[n_1] is high, the switch T4 is turned off. The enable signal EM[n] is used to enable the electronic units 150A and 150B. When the enable signal EM[n] is low, the switch T5 is turned on; when the enable signal EM[n] is high, the switch T5 is turned off. When the switch T5 is turned on, the data stored in the capacitor of the sub-circuit 160A can be transmitted to the electronic unit 150A, allowing the electronic unit 150A to operate based on the received data. The electronic unit 150A can be a light-emitting unit, a sensor, an antenna, or a radio frequency (RF) component. For example, if the electronic unit 150A is a light-emitting unit, when the switch T5 of the driving circuit 120A is turned on, the driving circuit 120A can drive the electronic unit 150A to emit light based on the data stored in the sub-circuit 160A. If the electronic unit 150A is a sensing unit, when the switch T5 of the driving circuit 120A is turned on, the driving circuit 120A can drive the electronic unit 150A to perform sensing operations based on the data stored in the sub-circuit 160A. Furthermore, if the electronic unit 150A is an RF component, when the switch T5 of the driving circuit 120A is turned on, the driving circuit 120A can drive the electronic unit 150A to transmit a radio signal based on the data stored in the sub-circuit 160A. The circuit structure of the driving circuit 120B is similar to that of the driving circuit 120A, and the driving circuit 120B comprises a switch T4, a switch T5, and a sub-circuit 160B. The difference between the two driving circuits 120A and 120B is that the gate of the switch T4 of the driving circuit 120B receives a switching signal SN[n 2], the second end of the switch T4 of the driving circuit 120B and the first end of the switch T5 of the driving circuit 120B are coupled to the sub-circuit 160B, and the second end of the switch T5 of the driving circuit 120B is coupled to the electronic unit 150B. In the embodiment, both switches T4 and T5 of the driving circuit 120B are P-type transistors. When the switching signal SN[n 2] is low, the switch T4 of the driving circuit 120B is turned on; when the switching signal SN[n 2] is high, the switch T4 of the driving circuit 120B is turned off. When the enable signal EM[n] is low, the switch T5 of the driving circuit 120B is turned on; when the enable signal EM[n] is high, the switch T5 of the driving circuit 120B is turned off. The electronic unit 150B can also be a light-emitting unit, a sensor, an antenna, or a radio frequency (RF) component.

In one embodiment of the present disclosure, when the electronic units 150A and 150B are light-emitting units, the circuit units 100A and 100B can be pixel circuit units for respectively driving the electronic units 150A and 150B to emit light.

In another embodiment, the electronic device 10A may further comprise circuit units 100C and 100D, and the four circuit units 100A, 100B, 100C, and 100D are arranged in proximity to each other. Among them, the circuit unit 100C comprises a time-interleaved circuit 110C, and the circuit unit 100D comprises a time-interleaved circuit 110D. The scan line 210A is coupled to the time-interleaved circuits 110A and 110C, and the scan line 210B is coupled to the time-interleaved circuits 110B and 110D. The circuit structure and coupling manner of the time-interleaved circuit 110C can be the same as that of the time-interleaved circuit 110A, and the circuit structure and coupling manner of the time-interleaved circuit 110D can be the same as that of the time-interleaved circuit 110B, which will not be described in detail herein.

Please refer to FIG. 1 to FIG. 3. FIG. 3 is a timing diagram of the electronic device 10A shown in FIG. 1. The clock signals Sw[1] and Sw[2] are not low at the same time. In phase I, the reset signal RST[n] is low, causing the switches T2 of both time-interleaved circuits 110A and 110B to be turned on, and thus resetting the potentials of both switching signals SN[n_1] and SN[n_2]. In phase II, the reset signal RST[n] is high and the scan signal SN[n] is low, causing the switches T1 of both time-interleaved circuits 110A and 110B to be turned on and the switches T2 of both time-interleaved circuits 110A and 110B to be turned off, resulting in the waveform of the switching signal SN[n_1] in phase II being the same as the waveform of the clock signal Sw[1] in phase II, and the waveform of the switching signal SN[n_2] in phase II being the same as the waveform of the clock signal Sw[2] in phase II. Since the two switching signals SN[n_1] and SN[n_2] are not low at the same time during phase II, the switch T4 of the driving circuit 120A and the switch T4 of the driving circuit 120B are turned on sequentially and not simultaneously, causing the data D1 and D2 on the data line 200 to be sampled sequentially at time points t1 and t2, respectively. As shown in FIG. 1, the data D1 sampled at time point t1 is transmitted to the circuit unit 100A, and the data D2 sampled at time point t2 is transmitted to the circuit unit 100B. Similarly, the circuit units 100C and 100D can sample the data on the data line 200 at time points t3 and t4, respectively, and obtain data D3 and D4, respectively. The data D3 sampled at time point t3 is transmitted to the circuit unit 100C, and the data D4 sampled at time point t4 is transmitted to the circuit unit 100D. The circuit unit 100C can drive the electronic unit 150C according to the data D3, and the circuit unit 100D can drive the electronic unit 150D according to the data D4. In phase III, both the reset signal RST[n] and the scan signal SN[n] are high, causing the switches T1 and T2 of both time-interleaved circuits 110A and 110B to be turned off.

The circuit structures of circuit units 100C and 100D can be identical to those of circuit units 100A and 100B in FIG. 2. The scan signals SN[n] received by the two circuit units 100C and 100D are not low at the same time as the scan signals SN[n] received by the two circuit units 100A and 100B. For example, the scan signals SN[n] received by the two circuit units 100C and 100D may not be low until a certain period in phase III after phase II in FIG. 3. In this way, the data on the data line 200 can be sampled by 100A, 100B, 100C, and 100D at the time points t1, t2, t3, and t4, respectively, resulting in data D1, D2, D3, and D4, respectively.

Please refer to FIG. 4 to FIG. 5. FIG. 4 is a partial circuit diagram of the electronic device 10B according to another embodiment of the present disclosure, and FIG. 5 is a timing diagram of the electronic device 10B shown in FIG. 4. The circuit architecture of the electronic device 10B is the same as that of the electronic device 10A, but the difference between the two electronic devices 10A and 10B lies in that the control ends (i.e., the gates of the two transistors) of the switches T2 in the two circuit units 100A and 100B of the electronic device 10B receive the enable signal EM[n]. In phase I of FIG. 5, the enable signal EM[n] is low, causing the switches T2 of both time-interleaved circuits 110A and 110B to be turned on, and thus resetting the potentials of both switching signals SN[n_1] and SN[n_2]. In phase II of FIG. 5, both the enable signal EM[n] and the scan signal SN[n] are high, causing the switches T1 and T2 of both time-interleaved circuits 110A and 110B to be turned off. In phase III of FIG. 5, the enable signal EM[n] is high and the scan signal SN[n] is low, causing the switches T1 of both time-interleaved circuits 110A and 110B to be turned on and the switches T2 of both time-interleaved circuits 110A and 110B to be turned off, resulting in the waveform of the switching signal SN[n_1] in phase III being the same as the waveform of the clock signal Sw[1] in phase III, and the waveform of the switching signal SN[n_2] in phase III being the same as the waveform of the clock signal Sw[2] in phase III. Since the two switching signals SN[n_1] and SN[n_2] are not low at the same time during phase III, the switch T4 of the driving circuit 120A and the switch T4 of the driving circuit 120B are turned on sequentially and not simultaneously, causing the data D1 and D2 on the data line 200 to be sampled sequentially at time points t1 and t2, respectively.

In one embodiment, the electronic unit 150A may comprise a light-emitting element E1, and the electronic unit 150B may comprise a light-emitting element E2. The light-emitting elements E1 and E2 may be light-emitting diodes, respectively.

Please refer to FIG. 6 to FIG. 7. FIG. 6 is a partial circuit diagram of the electronic device 10C according to another embodiment of the present disclosure, and FIG. 7 is a timing diagram of the electronic device 10C shown in FIG. 6. The circuit architecture of the electronic device 10C is the same as that of the electronic device 10A, but the difference between the two electronic devices 10C and 10A lies in that the control ends (i.e., the gates of the two transistors) of the switches T2 in the two circuit units 100A and 100B of the electronic device 10C receive a signal EMB[n], and the signal EMB[n] is not used to enable the switch T4, and the two switching signals SN[n_1] and SN[n_2] are only low when the signal EMB[n] is high. In phase I of FIG. 7, the signal EMB[n] is low, causing the switches T2 of both time-interleaved circuits 110A and 110B to be turned on, and thus resetting the potentials of both switching signals SN[n_1] and SN[n_2]. In phase II of FIG. 7, both the signal EMB[n] and the scan signal SN[n] are high, causing the switches T1 and T2 of both time-interleaved circuits 110A and 110B to be turned off. In phase III of FIG. 7, the signal EMB[n] is high and the scan signal SN[n] is low, causing the switches T1 of both time-interleaved circuits 110A and 110B to be turned on and the switches T2 of both time-interleaved circuits 110A and 110B to be turned off, resulting in the waveform of the switching signal SN[n_1] in phase III being the same as the waveform of the clock signal Sw[1] in phase III, and the waveform of the switching signal SN[n_2] in phase III being the same as the waveform of the clock signal Sw[2] in phase III. Since the two switching signals SN[n_1] and SN[n_2] are not low at the same time during phase III, the switch T4 of the driving circuit 120A and the switch T4 of the driving circuit 120B are turned on sequentially and not simultaneously, causing the data D1 and D2 on the data line 200 to be sampled sequentially at time points t1 and t2, respectively.

Please refer to FIG. 8. FIG. 8 is a partial circuit diagram of the electronic device 10D according to another embodiment of the present disclosure. The circuit architecture of the electronic device 10D is the same as that of the electronic device 10A, but the difference between the two electronic devices 10D and 10A lies in that, in addition to including all the components of the electronic device 10A, the two time-interleaved circuits 110A and 110B of the electronic device 10D each comprise a switch T3, and the junction A of the two transistors of the switch T1 in the time-interleaved circuit 110A and the control end (i.e., the gates of the two transistors) of the switch T2 are coupled to node A1, and the junction A of the two transistors of the switch T1 in the time-interleaved circuit 110B and the control end (i.e., the gates of the two transistors) of the switch T2 are coupled to node A2. The switches T3 of the two time-interleaved circuits 110A and 110B can be P-type transistors. Among them, the first end of the switch T3 in the time-interleaved circuit 110A is coupled to node A1, and the second end of the switch T3 in the time-interleaved circuit 110A is coupled to the control end (i.e., the gate) to receive the enable signal EM[n]. The first end of the switch T3 in the time-interleaved circuit 110B is coupled to node A2, and the second end of the switch T3 in the time-interleaved circuit 110B is coupled to the control end (i.e., the gate) to receive the enable signal EM[n]. The timing diagram of the signals of the electronic device 10D is as shown in FIG. 5. In phase I of FIG. 5, the enable signal EM[n] is low, causing the switches T3 of both time-interleaved circuits 110A and 110B to be turned on, causing the potential of node A1 to be low and causing the switches T2 of both time-interleaved circuits 110A and 110B to be turned on, thereby resetting the potentials of both switching signals SN[n_1] and SN[n_2]. In phase II of FIG. 5, both the enable signal EM[n] and the scan signal SN[n] are high, causing the switches T1 and T3 of both time-interleaved circuits 110A and 110B to be turned off. In phase III of FIG. 5, the enable signal EM[n] is high and the scan signal SN[n] is low, causing the switches T1 of both time-interleaved circuits 110A and 110B to be turned on, allowing the control end of the switch T2 in the time-interleaved circuit 110A and the switching signal SN[n_1] to have a waveform in phase III that is the same as the waveform of the clock signal Sw[1] in phase III; moreover, the control end of the switch T2 in the time-interleaved circuit 110B and the switching signal SN[n_2] can have a waveform in phase III that is the same as the waveform of the clock signal Sw[2] in phase III. Since the two switching signals SN[n_1] and SN[n_2] are not low at the same time during phase III, the switch T4 of the driving circuit 120A and the switch T4 of the driving circuit 120B are turned on sequentially and not simultaneously, causing the data D1 and D2 on the data line 200 to be sampled sequentially at time points t1 and t2, respectively.

The electronic device disclosed herein comprises two circuit units that can sample data from the same data line in a time-interleaved manner via time-interleaved circuits. In this way, the two circuit units can independently drive corresponding electronic units based on the data they have respectively sampled. Since the two circuit units share the same data line, the limited layout space of the electronic device can be effectively utilized.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.