San Jose, California
United States
32
2014-03-06
31
2014-10-28
These are the the leading inventors for applications assigned to SPRINGSOFT USA, INC.:
SPRINGSOFT USA, INC. based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio
#2 | 2013-04-11 ✅ Patent 10,152,482 granted on 2018-12-11Method of speeding up access to design databases having large numbers of design units
#3 | 2013-02-28 ✅ Patent 8,739,089 granted on 2014-05-27Systems and methods for increasing debugging visibility of prototyping systems
#4 | 2013-02-21 ✅ Patent 8,671,383 granted on 2014-03-11Viewing and debugging HDL designs having SystemVerilog interface constructs
#5 | 2012-11-29 ✅ Patent 8,607,182 granted on 2013-12-10Method of fast analog layout migration
#6 | 2012-10-23 ✅ Patent 8,296,708 granted on 2012-10-23Method of constraint-hierarchy-driven IC placement
#7 | 2012-09-20 ✅ Patent 9,053,264 granted on 2015-06-09What-if simulation methods and systems
#8 | 2012-07-12METHOD OF CONTEXT-SENSITIVE, TRANS-REFLEXIVE INCREMENTAL DESIGN RULE CHECKING AND ITS APPLICATIONS
#9 | 2012-04-05 ✅ Patent 8,359,560 granted on 2013-01-22Methods and systems for debugging equivalent designs described at different design levels
#10 | 2012-03-15 ✅ Patent 8,789,008 granted on 2014-07-22Methods for generating device layouts by combining an automated device layout generator with a script
#11 | 2011-12-29 ✅ Patent 8,365,132 granted on 2013-01-29Hierarchial power map for low power design
#12 | 2011-12-08 ✅ Patent 8,359,559 granted on 2013-01-22Methods and systems for evaluating checker quality of a verification environment
#13 | 2011-10-13 ✅ Patent 8,255,853 granted on 2012-08-28Circuit emulation systems and methods
#14 | 2011-08-18 ✅ Patent 8,261,223 granted on 2012-09-04Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit
#15 | 2011-08-18 ✅ Patent 8,281,280 granted on 2012-10-02Method and apparatus for versatile controllability and observability in prototype system
#16 | 2011-06-23 ✅ Patent 8,407,647 granted on 2013-03-26Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio
#17 | 2011-03-29 ✅ Patent 7,917,881 granted on 2011-03-29Timing of a circuit design
#18 | 2010-09-23 ✅ Patent 9,183,329 granted on 2015-11-10Debugging simulation with partial design replay
#19 | 2010-09-09 ✅ Patent 8,086,982 granted on 2011-12-27Methods and systems for reducing clock skew in a gated clock tree
#20 | 2010-07-29 ✅ Patent 8,176,453 granted on 2012-05-08Power-aware debugging
#21 | 2010-06-15 ✅ Patent 7,739,630 granted on 2010-06-15Optimizing a circuit design
#22 | 2010-03-04 ✅ Patent 8,311,793 granted on 2012-11-13Method for evaluating a test program quality
#23 | 2009-09-17 ✅ Patent 7,873,928 granted on 2011-01-18Hierarchical analog IC placement subject to symmetry, matching and proximity constraints
#24 | 2009-09-03 ✅ Patent 8,010,919 granted on 2011-08-30Method for evaluating the quality of a computer program
#25 | 2009-07-09 ✅ Patent 8,015,522 granted on 2011-09-06System for implementing post-silicon IC design changes
#26 | 2009-04-30 ✅ Patent 7,877,718 granted on 2011-01-25Analog IC placement using symmetry-islands
#27 | 2009-01-29 ✅ Patent 7,984,410 granted on 2011-07-19Hierarchy-based analytical placement method for an integrated circuit
#28 | 2007-12-13 ✅ Patent 7,779,379 granted on 2010-08-17Template-based gateway model routing system
#29 | 2007-11-15 ✅ Patent 7,574,681 granted on 2009-08-11Method and system for evaluating computer program tests by means of mutation analysis
#30 | 2007-11-01 ✅ Patent 7,707,536 granted on 2010-04-27V-shaped multilevel full-chip gridless routing
#31 | 2007-07-26 ✅ Patent 7,478,346 granted on 2009-01-13Debugging system for gate level IC designs
#32 | 2007-05-10 ✅ Patent 7,571,086 granted on 2009-08-04Incremental circuit re-simulation system
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