Assignee profile:

MoSys, Inc.

City:

Sunnyvale, California

Country:

United States

Published Applications:

39

Last publication date:

2012-03-01

Patent Grants:

32

Last grant date:

2013-05-07

Top Inventors for applications by MoSys, Inc.

These are the the leading inventors for applications assigned to MoSys, Inc.:

Recent patent applications by MoSys, Inc.

MoSys, Inc. based in Sunnyvale, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:

#1 | 2012-03-01 ✅ Patent 8,436,660 granted on 2013-05-07
US20120054704A1
Electricity

Voltage-mode driver with equalization

#2 | 2011-09-08
US20110216596A1
Physics

Reliability Protection for Non-Volatile Memories

#3 | 2011-08-04 ✅ Patent 8,832,336 granted on 2014-09-09
US20110191619A1
Physics

Reducing latency in serializer-deserializer links

#4 | 2011-08-04 ✅ Patent 8,539,196 granted on 2013-09-17
US20110191564A1
Physics

Hierarchical organization of large memory blocks

#5 | 2011-08-04 ✅ Patent 9,342,471 granted on 2016-05-17
US20110191548A1
Physics

High utilization multi-partitioned serial memory

#6 | 2011-08-04 ✅ Patent 8,547,774 granted on 2013-10-01
US20110188335A1
Physics

Hierarchical multi-bank multi-port memory organization

#7 | 2011-06-23 ✅ Patent 8,526,265 granted on 2013-09-03
US20110149673A1
Physics

Three state word line driver for a DRAM memory device

#8 | 2011-04-14 ✅ Patent 8,139,399 granted on 2012-03-20
US20110085398A1
Physics

Multiple cycle memory write completion

#9 | 2010-10-28
US20100275170A1
Physics

Porting Analog Circuit Designs

#10 | 2010-10-28 ✅ Patent 8,269,538 granted on 2012-09-18
US20100271094A1
Physics

Signal alignment system

#11 | 2010-09-16 ✅ Patent 8,171,234 granted on 2012-05-01
US20100235590A1
Physics

Multi-bank multi-port architecture

#12 | 2010-08-19 ✅ Patent 8,081,521 granted on 2011-12-20
US20100208530A1
Physics

Two bits per cell non-volatile memory architecture

#13 | 2010-08-12 ✅ Patent 8,161,355 granted on 2012-04-17
US20100205504A1
Physics

Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process

#14 | 2010-08-12 ✅ Patent 7,894,270 granted on 2011-02-22
US20100202203A1
Physics

Data restoration method for a non-volatile memory

#15 | 2010-06-10
US20100140680A1
Electricity

Double Polysilicon Process for Non-Volatile Memory

#16 | 2010-05-13 ✅ Patent 8,361,863 granted on 2013-01-29
US20100120213A1
Electricity

Embedded DRAM with multiple gate oxide thicknesses

#17 | 2010-05-13 ✅ Patent 7,929,359 granted on 2011-04-19
US20100118596A1
Electricity

Embedded DRAM with bias-independent capacitance

#18 | 2009-12-15 ✅ Patent 7,634,707 granted on 2009-12-15
US10800382
-

Error detection/correction method

#19 | 2008-09-04 ✅ Patent 7,728,747 granted on 2010-06-01
US20080211702A1
Electricity

Comparator chain offset reduction

#20 | 2008-08-28
US20080209303A1
Electricity

Error Detection/Correction Method

#21 | 2008-08-07 ✅ Patent 7,633,811 granted on 2009-12-15
US20080186778A1
Electricity

Non-volatile memory embedded in a conventional logic process and methods for operating same

#22 | 2008-07-03 ✅ Patent 7,791,975 granted on 2010-09-07
US20080159036A1
Physics

Scalable embedded DRAM array

#23 | 2008-07-03 ✅ Patent 7,684,229 granted on 2010-03-23
US20080158929A1
Physics

Scalable embedded DRAM array

#24 | 2008-06-26
US20080153225A1
Physics

Non-Volatile Memory In CMOS Logic Process

#25 | 2008-06-26
US20080151623A1
Physics

Non-Volatile Memory In CMOS Logic Process

#26 | 2008-06-12 ✅ Patent 7,919,367 granted on 2011-04-05
US20080138950A1
Electricity

Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process

#27 | 2008-06-12 ✅ Patent 7,633,810 granted on 2009-12-15
US20080137438A1
Electricity

Non-volatile memory embedded in a conventional logic process and methods for operating same

#28 | 2008-06-12 ✅ Patent 7,477,546 granted on 2009-01-13
US20080137437A1
Electricity

Non-volatile memory embedded in a conventional logic process and methods for operating same

#29 | 2008-06-12 ✅ Patent 7,522,456 granted on 2009-04-21
US20080137410A1
Electricity

Non-volatile memory embedded in a conventional logic process and methods for operating same

#30 | 2008-04-24
US20080093645A1
Electricity

Fabrication Process For Increased Capacitance In An Embedded DRAM Memory

#31 | 2008-01-03 ✅ Patent 7,533,222 granted on 2009-05-12
US20080005492A1
Physics

Dual-port SRAM memory using single-port memory cell

#32 | 2007-12-06 ✅ Patent 7,382,658 granted on 2008-06-03
US20070279987A1
Electricity

Non-volatile memory embedded in a conventional logic process and methods for operating same

#33 | 2007-10-25 ✅ Patent 7,391,647 granted on 2008-06-24
US20070247914A1
Physics

Non-volatile memory in CMOS logic process and method of operation thereof

#34 | 2007-05-17 ✅ Patent 7,447,104 granted on 2008-11-04
US20070109906A1
Physics

Word line driver for DRAM embedded in a logic process

#35 | 2007-05-03 ✅ Patent 7,671,401 granted on 2010-03-02
US20070097743A1
Physics

Non-volatile memory in CMOS logic process

#36 | 2007-03-29 ✅ Patent 7,499,307 granted on 2009-03-03
US20070070759A1
Physics

Scalable embedded DRAM array

#37 | 2006-08-03 ✅ Patent 7,323,379 granted on 2008-01-29
US20060172504A1
Electricity

Fabrication process for increased capacitance in an embedded DRAM memory

#38 | 2006-06-08 ✅ Patent 7,392,456 granted on 2008-06-24
US20060123322A1
Physics

Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory

#39 | 2005-02-24 ✅ Patent 7,353,438 granted on 2008-04-01
US20050044467A1
Physics

Transparent error correcting memory

AssigneeID:

177664 ⎘