Assignee profile:

CHIPMOS TECHNOLOGIES (BERMUDA) LTD.

City:

Hamilton

Country:

Bermuda

Published Applications:

85

Last publication date:

2011-12-08

Patent Grants:

76

Last grant date:

2012-09-18

Top Inventors for applications by CHIPMOS TECHNOLOGIES (BERMUDA) LTD.

These are the the leading inventors for applications assigned to CHIPMOS TECHNOLOGIES (BERMUDA) LTD.:

Recent patent applications by CHIPMOS TECHNOLOGIES (BERMUDA) LTD.

CHIPMOS TECHNOLOGIES (BERMUDA) LTD. based in Hamilton, BM has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:

#1 | 2011-12-08 ✅ Patent 8,268,717 granted on 2012-09-18
US20110300705A1
Electricity

Manufacturing method of bump structure with annular support

#2 | 2011-07-28 ✅ Patent 8,426,245 granted on 2013-04-23
US20110183467A1
Electricity

Packaging method involving rearrangement of dice

#3 | 2011-07-28 ✅ Patent 8,431,437 granted on 2013-04-30
US20110183466A1
Electricity

Packaging method involving rearrangement of dice

#4 | 2010-12-16 ✅ Patent 8,207,603 granted on 2012-06-26
US20100314729A1
Electricity

Stacked chip package structure with leadframe having inner leads with transfer pad

#5 | 2010-10-21 ✅ Patent 8,169,061 granted on 2012-05-01
US20100264530A1
Electricity

Stacked chip package structure with leadframe having bus bar

#6 | 2010-10-21 ✅ Patent 8,212,347 granted on 2012-07-03
US20100264527A1
Electricity

Stacked chip package structure with leadframe having bus bar

#7 | 2010-09-30 ✅ Patent 8,237,249 granted on 2012-08-07
US20100244278A1
Electricity

Stacked multichip package

#8 | 2010-08-12 ✅ Patent 7,952,198 granted on 2011-05-31
US20100200972A1
Electricity

BGA package with leads on chip

#9 | 2010-07-29 ✅ Patent 7,919,874 granted on 2011-04-05
US20100187692A1
Electricity

Chip package without core and stacked chip package structure

#10 | 2010-07-29
US20100187691A1
Electricity

CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE

#11 | 2010-07-15 ✅ Patent 7,879,653 granted on 2011-02-01
US20100178734A1
Electricity

Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same

#12 | 2010-06-24 ✅ Patent 7,888,783 granted on 2011-02-15
US20100155916A1
Electricity

Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers

#13 | 2010-06-17 ✅ Patent 7,981,725 granted on 2011-07-19
US20100151624A1
Electricity

Fabricating process of a chip package structure

#14 | 2010-05-27 ✅ Patent 7,843,054 granted on 2010-11-30
US20100127367A1
Electricity

Chip package and manufacturing method thereof

#15 | 2010-04-08 ✅ Patent 7,915,690 granted on 2011-03-29
US20100084759A1
Electricity

Die rearrangement package structure using layout process to form a compliant configuration

#16 | 2010-04-01 ✅ Patent 8,039,946 granted on 2011-10-18
US20100078802A1
Electricity

Chip package structure and fabricating method thereof

#17 | 2009-12-10 ✅ Patent 7,888,172 granted on 2011-02-15
US20090302448A1
Electricity

Chip stacked structure and the forming method

#18 | 2009-11-12 ✅ Patent 8,088,650 granted on 2012-01-03
US20090280603A1
Electricity

Method of fabricating chip package

#19 | 2009-10-01 ✅ Patent 7,834,432 granted on 2010-11-16
US20090243056A1
Electricity

Chip package having asymmetric molding

#20 | 2009-09-24 ✅ Patent 7,700,412 granted on 2010-04-20
US20090236703A1
Electricity

Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers

#21 | 2009-08-20 ✅ Patent 8,421,223 granted on 2013-04-16
US20090206476A1
Electricity

Conductive structure for a semiconductor integrated circuit

#22 | 2009-08-06 ✅ Patent 7,741,149 granted on 2010-06-22
US20090197374A1
Electricity

Method of fabricating chip package structure

#23 | 2009-06-25 ✅ Patent 7,662,667 granted on 2010-02-16
US20090160071A1
Electricity

Die rearrangement package structure using layout process to form a compliant configuration

#24 | 2009-06-25 ✅ Patent 7,927,922 granted on 2011-04-19
US20090160043A1
Electricity

Dice rearrangement package structure using layout process to form a compliant configuration

#25 | 2009-05-21 ✅ Patent 7,648,902 granted on 2010-01-19
US20090130839A1
Electricity

Manufacturing method of redistribution circuit structure

#26 | 2009-03-12 ✅ Patent 7,795,079 granted on 2010-09-14
US20090068799A1
Electricity

Manufacturing process for a quad flat non-leaded chip package structure

#27 | 2009-03-12
US20090068797A1
Electricity

MANUFACTURING PROCESS FOR A QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE

#28 | 2009-03-12 ✅ Patent 7,803,667 granted on 2010-09-28
US20090068794A1
Electricity

Manufacturing process for a quad flat non-leaded chip package structure

#29 | 2009-03-12 ✅ Patent 7,790,514 granted on 2010-09-07
US20090068793A1
Electricity

Manufacturing process for a chip package structure

#30 | 2009-03-12 ✅ Patent 7,851,270 granted on 2010-12-14
US20090068792A1
Electricity

Manufacturing process for a chip package structure

#31 | 2009-03-12 ✅ Patent 7,851,262 granted on 2010-12-14
US20090068789A1
Electricity

Manufacturing process for a chip package structure

#32 | 2009-03-12 ✅ Patent 7,964,940 granted on 2011-06-21
US20090065913A1
Electricity

Chip package with asymmetric molding

#33 | 2009-03-12 ✅ Patent 7,803,666 granted on 2010-09-28
US20090064494A1
Electricity

Manufacturing process for a Quad Flat Non-leaded chip package structure

#34 | 2009-02-19
US20090047754A1
Electricity

PACKAGING METHOD INVOLVING REARRANGEMENT OF DICE

#35 | 2009-01-29
US20090026632A1
Electricity

CHIP-TO-CHIP PACKAGE AND PROCESS THEREOF

#36 | 2008-12-25 ✅ Patent 7,851,896 granted on 2010-12-14
US20080315439A1
Electricity

Quad flat non-leaded chip package

#37 | 2008-12-18 ✅ Patent 7,638,880 granted on 2009-12-29
US20080308916A1
Electricity

Chip package

#38 | 2008-12-18
US20080308914A1
Electricity

CHIP PACKAGE

#39 | 2008-12-11 ✅ Patent 7,723,853 granted on 2010-05-25
US20080303174A1
Electricity

Chip package without core and stacked chip package structure

#40 | 2008-10-30 ✅ Patent 7,960,214 granted on 2011-06-14
US20080268572A1
Electricity

Chip package

#41 | 2008-10-30 ✅ Patent 7,749,806 granted on 2010-07-06
US20080268570A1
Electricity

Fabricating process of a chip package structure

#42 | 2008-10-16 ✅ Patent 7,847,414 granted on 2010-12-07
US20080251948A1
Electricity

Chip package structure

#43 | 2008-09-18
US20080224284A1
Electricity

CHIP PACKAGE STRUCTURE

#44 | 2008-08-14
US20080191324A1
Electricity

CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

#45 | 2008-08-07 ✅ Patent 8,105,881 granted on 2012-01-31
US20080188039A1
Electricity

Method of fabricating chip package structure

#46 | 2008-08-07 ✅ Patent 7,683,462 granted on 2010-03-23
US20080185697A1
Electricity

Chip package structure

#47 | 2008-07-17 ✅ Patent 8,030,767 granted on 2011-10-04
US20080169559A1
Electricity

Bump structure with annular support

#48 | 2008-07-17 ✅ Patent 7,498,251 granted on 2009-03-03
US20080169558A1
Electricity

Redistribution circuit structure

#49 | 2008-05-01 ✅ Patent 7,816,771 granted on 2010-10-19
US20080099896A1
Electricity

Stacked chip package structure with leadframe having inner leads with transfer pad

#50 | 2008-05-01 ✅ Patent 7,663,246 granted on 2010-02-16
US20080099892A1
Electricity

Stacked chip packaging with heat sink structure

#51 | 2008-04-24
US20080093719A1
Electricity

CHIP PACKAGE STRUCTURE

#52 | 2008-04-10 ✅ Patent 7,936,032 granted on 2011-05-03
US20080085038A1
Physics

Film type package for fingerprint sensor

#53 | 2008-03-13 ✅ Patent 7,786,595 granted on 2010-08-31
US20080061421A1
Electricity

Stacked chip package structure with leadframe having bus bar

#54 | 2008-03-13 ✅ Patent 7,615,853 granted on 2009-11-10
US20080061412A1
Electricity

Chip-stacked package structure having leadframe with multi-piece bus bar

#55 | 2008-02-14 ✅ Patent 7,582,953 granted on 2009-09-01
US20080036067A1
Electricity

Package structure with leadframe on offset chip-stacked structure

#56 | 2008-01-24 ✅ Patent 7,514,299 granted on 2009-04-07
US20080017961A1
Electricity

Chip package structure and manufacturing method thereof

#57 | 2008-01-24 ✅ Patent 7,361,984 granted on 2008-04-22
US20080017958A1
Electricity

Chip package structure

#58 | 2008-01-17 ✅ Patent 7,528,495 granted on 2009-05-05
US20080012150A1
Electricity

Chip structure

#59 | 2008-01-10 ✅ Patent 7,405,144 granted on 2008-07-29
US20080009085A1
Physics

Method for manufacturing probe card

#60 | 2008-01-10 ✅ Patent 7,446,400 granted on 2008-11-04
US20080006917A1
Electricity

Chip package structure and fabricating method thereof

#61 | 2007-11-15 ✅ Patent 7,642,639 granted on 2010-01-05
US20070262439A1
Electricity

COB type IC package to enhanced bondibility of bumps embedded in substrate and method for fabricating the same

#62 | 2007-10-11 ✅ Patent 7,554,197 granted on 2009-06-30
US20070235871A1
Electricity

High frequency IC package and method for fabricating the same

#63 | 2007-10-04
US20070228555A1
Electricity

Semiconductor chip having fine pitch bumps and bumps thereon

#64 | 2007-09-20 ✅ Patent 7,579,676 granted on 2009-08-25
US20070215995A1
Electricity

Leadless leadframe implemented in a leadframe-based BGA package

#65 | 2007-09-06 ✅ Patent 7,651,886 granted on 2010-01-26
US20070207608A1
Electricity

Semiconductor device and manufacturing process thereof

#66 | 2007-07-05 ✅ Patent 7,372,286 granted on 2008-05-13
US20070152689A1
Physics

Modular probe card

#67 | 2007-06-21 ✅ Patent 7,538,435 granted on 2009-05-26
US20070141824A1
Electricity

Wafer structure and bumping process

#68 | 2007-04-26 ✅ Patent 7,586,200 granted on 2009-09-08
US20070090388A1
Electricity

Light emitting diode chip with reflective layer thereon

#69 | 2007-04-19 ✅ Patent 7,385,282 granted on 2008-06-10
US20070085186A1
Electricity

Stacked-type chip package structure

#70 | 2007-04-19 ✅ Patent 7,576,416 granted on 2009-08-18
US20070085176A1
Electricity

Chip package having with asymmetric molding and turbulent plate downset design

#71 | 2007-04-19 ✅ Patent 7,622,806 granted on 2009-11-24
US20070084836A1
Electricity

Laser mark on an IC component

#72 | 2007-04-12 ✅ Patent 7,443,013 granted on 2008-10-28
US20070080432A1
Electricity

Flexible substrate for package of die

#73 | 2007-03-29 ✅ Patent 7,477,065 granted on 2009-01-13
US20070069750A1
Physics

Method for fabricating a plurality of elastic probes in a row

#74 | 2007-02-01 ✅ Patent 7,504,714 granted on 2009-03-17
US20070023872A1
Electricity

Chip package with asymmetric molding

#75 | 2007-01-30 ✅ Patent 7,170,160 granted on 2007-01-30
US11301860
-

Chip structure and stacked-chip package

#76 | 2007-01-25 ✅ Patent 7,560,306 granted on 2009-07-14
US20070020816A1
Electricity

Manufacturing process for chip package without core

#77 | 2007-01-18 ✅ Patent 7,436,074 granted on 2008-10-14
US20070013043A1
Electricity

Chip package without core and stacked chip package structure thereof

#78 | 2006-09-21 ✅ Patent 7,370,416 granted on 2008-05-13
US20060211273A1
Chemistry; metallurgy

Method of manufacturing an injector plate

#79 | 2006-06-15 ✅ Patent 7,129,730 granted on 2006-10-31
US20060125501A1
Physics

Probe card assembly

#80 | 2006-06-15 ✅ Patent 7,088,118 granted on 2006-08-08
US20060125498A1
Physics

Modularized probe card for high frequency probing

#81 | 2006-03-02 ✅ Patent 7,696,443 granted on 2010-04-13
US20060042834A1
Electricity

Electronic device with a warped spring connector

#82 | 2006-02-28 ✅ Patent 7,005,054 granted on 2006-02-28
US10223350
-

Method for manufacturing probes of a probe card

#83 | 2005-04-28 ✅ Patent 6,946,860 granted on 2005-09-20
US20050088190A1
Physics

Modularized probe head

#84 | 2005-03-31 ✅ Patent 7,140,101 granted on 2006-11-28
US20050066521A1
Electricity

Method for fabricating anisotropic conductive substrate

#85 | 2005-01-20 ✅ Patent 6,853,205 granted on 2005-02-08
US20050012513A1
Physics

Probe card assembly

Also check out ChipMOS Technologies (Bermuda) Ltd.'s (Hamilton, Bermuda) applicant profile with 2 patent applications submitted.

AssigneeID:

209955 ⎘