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Assignee profile:

LogicVision, Inc.

City:

San Jose, California

Country:

United States

Published Applications:

24

Last publication date:

2010-02-11

Patent Grants:

21

Last grant date:

2010-07-13

Top Inventors for applications by LogicVision, Inc.

These are the the leading inventors for applications assigned to LogicVision, Inc.:

Recent patent applications by LogicVision, Inc.

LogicVision, Inc. based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:

#1 | 2010-02-11
US20100037109A1
Physics

METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN

 #2 | 2008-03-13 ✅ Patent 7,757,135 granted on 2010-07-13
US20080065929A1
Physics

Method and apparatus for storing and distributing memory repair information

 #3 | 2007-11-15 ✅ Patent 7,617,425 granted on 2009-11-10
US20070266278A1
Physics

Method for at-speed testing of memory interface using scan

 #4 | 2007-08-14 ✅ Patent 7,257,733 granted on 2007-08-14
US10868208
-

Memory repair circuit and method

 #5 | 2007-05-15 ✅ Patent 7,219,282 granted on 2007-05-15
US10701479
-

Boundary scan with strobed pad driver enable

 #6 | 2007-03-20 ✅ Patent 7,194,669 granted on 2007-03-20
US10739055
-

Method and circuit for at-speed testing of scan circuits

 #7 | 2007-03-13 ✅ Patent 7,191,374 granted on 2007-03-13
US10435094
-

Method of and program product for performing gate-level diagnosis of failing vectors

 #8 | 2007-03-06 ✅ Patent 7,188,274 granted on 2007-03-06
US10774512
-

Memory repair analysis method and circuit

 #9 | 2007-01-02 ✅ Patent 7,159,159 granted on 2007-01-02
US10414309
-

Circuit and method for adding parametric test capability to digital boundary scan

 #10 | 2006-11-21 ✅ Patent 7,139,946 granted on 2006-11-21
US10638388
-

Method and test circuit for testing memory internal write enable

 #11 | 2006-09-05 ✅ Patent 7,103,860 granted on 2006-09-05
US10349452
-

Verification of embedded test structures in circuit designs

 #12 | 2005-12-08
US20050273683A1
Physics

Insertion of embedded test in RTL to GDSII flow

 #13 | 2005-11-01 ✅ Patent 6,961,871 granted on 2005-11-01
US9954078
-

Method, system and program product for testing and/or diagnosing circuits using embedded test controller access data

 #14 | 2005-10-27
US20050240848A1
Physics

Masking circuit and method of masking corrupted bits

 #15 | 2005-10-27 ✅ Patent 7,155,651 granted on 2006-12-26
US20050240847A1
Physics

Clock controller for at-speed testing of scan circuits

 #16 | 2005-10-27 ✅ Patent 7,424,656 granted on 2008-09-09
US20050240790A1
Physics

Clocking methodology for at-speed testing of scan circuits with synchronous clocks

 #17 | 2005-05-26 ✅ Patent 7,453,255 granted on 2008-11-18
US20050111537A1
Physics

Circuit and method for measuring delay of high speed signals

 #18 | 2005-05-17 ✅ Patent 6,895,535 granted on 2005-05-17
US10727583
-

Circuit and method for testing high speed data circuits

 #19 | 2005-04-26 ✅ Patent 6,885,213 granted on 2005-04-26
US10634902
-

Circuit and method for accurately applying a voltage to a node of an integrated circuit

 #20 | 2005-04-19 ✅ Patent 6,883,134 granted on 2005-04-19
US9817299
-

Method and program product for detecting bus conflict and floating bus conditions in circuit designs

 #21 | 2005-03-31 ✅ Patent 7,158,899 granted on 2007-01-02
US20050069031A1
Electricity

Circuit and method for measuring jitter of high speed signals

 #22 | 2005-03-15 ✅ Patent 6,868,532 granted on 2005-03-15
US10011128
-

Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby

 #23 | 2005-03-03 ✅ Patent 7,370,251 granted on 2008-05-06
US20050047229A1
Physics

Method and circuit for collecting memory failure information

 #24 | 2005-03-01 ✅ Patent 6,862,717 granted on 2005-03-01
US10015751
-

Method and program product for designing hierarchical circuit for quiescent current testing
AssigneeID:

232148 ⎘