Sunnyvale, California
United States
17
2008-01-03
17
2009-05-12
These are the the leading inventors for applications assigned to MONOLITHIC SYSTEM TECHNOLOGY, INC.:
MONOLITHIC SYSTEM TECHNOLOGY, INC. based in Sunnyvale, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Dual-port SRAM memory using single-port memory cell
#2 | 2007-12-06 ✅ Patent 7,382,658 granted on 2008-06-03Non-volatile memory embedded in a conventional logic process and methods for operating same
#3 | 2007-10-25 ✅ Patent 7,391,647 granted on 2008-06-24Non-volatile memory in CMOS logic process and method of operation thereof
#4 | 2007-05-17 ✅ Patent 7,447,104 granted on 2008-11-04Word line driver for DRAM embedded in a logic process
#5 | 2007-05-03 ✅ Patent 7,671,401 granted on 2010-03-02Non-volatile memory in CMOS logic process
#6 | 2007-03-29 ✅ Patent 7,499,307 granted on 2009-03-03Scalable embedded DRAM array
#7 | 2006-12-28 ✅ Patent 7,274,618 granted on 2007-09-25Word line driver for DRAM embedded in a logic process
#8 | 2006-08-03 ✅ Patent 7,323,379 granted on 2008-01-29Fabrication process for increased capacitance in an embedded DRAM memory
#9 | 2006-06-08 ✅ Patent 7,392,456 granted on 2008-06-24Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
#10 | 2006-05-25 ✅ Patent 7,275,200 granted on 2007-09-25Transparent error correcting memory that supports partial-word write
#11 | 2006-05-23 ✅ Patent 7,051,264 granted on 2006-05-23Error correcting memory and method of operating same
#12 | 2005-11-15 ✅ Patent 6,964,895 granted on 2005-11-15Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
#13 | 2005-07-05 ✅ Patent 6,913,964 granted on 2005-07-05Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
#14 | 2005-05-24 ✅ Patent 6,898,140 granted on 2005-05-24Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
#15 | 2005-04-07 ✅ Patent 7,056,785 granted on 2006-06-06Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
#16 | 2005-02-03 ✅ Patent 7,206,913 granted on 2007-04-17High speed memory system
#17 | 2005-01-11 ✅ Patent 6,841,821 granted on 2005-01-11Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
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