Integrated Device Technology, Inc.

Integrated circuits and methods with transmit-side data bus deskew

Integrated circuits and methods with statistics-based input data signal sample timing

Timer rollover handling mechanism for traffic policing

Fast collision detection for a hashed content addressable memory (CAM) using a random access memory

Memory array bit line coupling capacitor cancellation

Partial packet write and write data filtering in a multi-queue first-in first-out memory system

Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system

Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system

Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system

Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system

Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system

Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system

Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system

Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews

Memory device layout

Content addressable memory (CAM) devices with block select and pipelined virtual sector look-up control and methods of operating same

Content addressable memory (CAM) devices that utilize segmented match lines and word lines to support pipelined search and write operations and methods of operating same

Content addressable memory (CAM) devices that utilize dual-capture match line signal repeaters to achieve desired speed/power tradeoff and methods of operating same

Integrated circuit devices having high precision digital delay lines therein

Grid array microelectronic packages with increased periphery

CAM circuit with radiation resistance

Edge accelerated sense amplifier flip-flop with high fanout drive capability

Content addressable memory (CAM) devices having scalable multiple match detection circuits therein

DRAM-based CAM cell with shared bitlines

Dual-wavelength exposure for reduction of implant shadowing

Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratio

Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same

Methods, apparatus and computer program products for modeling integrated circuit devices having reduced linewidths

Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control

SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same

Nitrogen implementation to minimize device variation

Content addressable and random access memory devices having high-speed sense amplifiers therein with low power consumption requirements

Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same

FIFO memory devices having multi-port cache and extended capacity memory devices therein with retransmit capability

Multi-step tungsten etchback process to preserve barrier integrity in an integrated circuit structure

Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors

Integrated circuit random access memory capable of automatic internal refresh of memory array

Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics

Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments

Content addressable memory devices with virtual partitioning and methods of operating the same

Apparatus and method for transferring multi-byte words in a fly-by DMA operation

Packaged semiconductor device having stacked die

Etch stop layer for use in a self-aligned contact etch

Multiple match detection logic and gates for content addressable memory (CAM) devices

Precise voltage/current reference circuit using current-mode technique in CMOS technology

Integrated circuit devices having high precision digital delay lines therein

Nitrogen implementation to minimize device variation

Content addressable memory (CAM) devices having dedicated mask cell sub-arrays therein and methods of operating same