Mountain View, California
United States
18
2026-05-21
2
2025-12-09
These are the the leading inventors for applications assigned to Ascenium, Inc.:
Ascenium, Inc. based in Mountain View, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
GENERATING ITERATION TRANSFER INFORMATION FOR CODE EXECUTION WITH A COMPUTE SLICE MICROARCHITECTURE
#2 | 2025-12-18MEMORY DEPENDENCE PREDICTION IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES
#3 | 2025-11-06GLOBAL MEMORY DISAMBIGUATION FOR A PARALLEL ARCHITECTURE WITH COMPUTE SLICES
#4 | 2025-10-02LOCAL MEMORY DISAMBIGUATION FOR A PARALLEL ARCHITECTURE WITH COMPUTE SLICES
#5 | 2025-08-21COMPILER GENERATED HYPERBLOCKS IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES
#6 | 2025-03-13SEMANTIC ORDERING FOR PARALLEL ARCHITECTURE WITH COMPUTE SLICES
#7 | 2025-01-16PARALLEL ARCHITECTURE WITH COMPILER-SCHEDULED COMPUTE SLICES
#8 | 2024-12-19PARALLEL PROCESSING ARCHITECTURE WITH BLOCK MOVE BACKPRESSURE
#9 | 2024-11-21PARALLEL PROCESSING ARCHITECTURE WITH BLOCK MOVE SUPPORT
#10 | 2024-08-08PARALLEL PROCESSING HAZARD MITIGATION AVOIDANCE
#11 | 2024-06-13PARALLEL PROCESSING ARCHITECTURE FOR BRANCH PATH SUPPRESSION
#12 | 2024-05-23PARALLEL PROCESSING WITH HAZARD DETECTION AND STORE PROBES
#13 | 2024-03-07PARALLEL PROCESSING WITH SWITCH BLOCK EXECUTION
#14 | 2024-02-29 ✅ Patent 12,493,554 granted on 2025-12-09PARALLEL PROCESSING USING HAZARD DETECTION AND MITIGATION
#15 | 2024-01-25PARALLEL PROCESSING ARCHITECTURE WITH BIN PACKING
#16 | 2023-12-21PARALLEL PROCESSING ARCHITECTURE WITH MEMORY BLOCK TRANSFERS
#17 | 2023-11-23PARALLEL PROCESSING ARCHITECTURE WITH DUAL LOAD BUFFERS
#18 | 2022-09-15 ✅ Patent 12,578,991 granted on 2026-03-17PARALLEL PROCESSING ARCHITECTURE WITH DISTRIBUTED REGISTER FILES
Also check out Ascenium, Inc.'s (Mountain View, United States) applicant profile with 14 patent applications submitted.
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