Santa Clara, California
United States
175
2020-06-02
170
2020-06-02
These are the the leading inventors for applications assigned to Netronome Systems, Inc.:
Netronome Systems, Inc. based in Santa Clara, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Network interface device that sets an ECN-CE bit in response to detecting congestion at an internal bus interface
#2 | 2020-06-02 β Patent 10,671,530 granted on 2020-06-02High-speed and memory-efficient flow cache for network flow processors
#3 | 2020-05-19 β Patent 10,659,030 granted on 2020-05-19Transactional memory that performs a statistics add-and-update operation
#4 | 2019-12-03 β Patent 10,496,625 granted on 2019-12-03Ordering system that employs chained ticket release bitmap having a protected portion
#5 | 2019-11-12 β Patent 10,476,747 granted on 2019-11-12Loading a flow tracking autolearning match table
#6 | 2019-09-17 β Patent 10,419,242 granted on 2019-09-17Low-level programming language plugin to augment high-level programming language setup of an SDN switch
#7 | 2019-07-30 β Patent 10,366,019 granted on 2019-07-30Multiprocessor system having efficient and shared atomic metering resource
#8 | 2019-07-30 β Patent 10,365,681 granted on 2019-07-30Multiprocessor system having fast clocking prefetch circuits that cause processor clock signals to be gapped
#9 | 2019-07-02 β Patent 10,341,246 granted on 2019-07-02Update packet sequence number packet ready command
#10 | 2019-02-12 β Patent 10,204,046 granted on 2019-02-12High-speed and memory-efficient flow cache for network flow processors
#11 | 2019-01-29 β Patent 10,191,867 granted on 2019-01-29Multiprocessor system having posted transaction bus interface that generates posted transaction bus commands
#12 | 2019-01-10 β Patent 10,318,334 granted on 2019-06-11Virtio relay
#13 | 2018-11-29 β Patent 10,230,638 granted on 2019-03-12Executing a selected sequence of instructions depending on packet type in an exact-match flow switch
#14 | 2018-11-15 β Patent 10,680,943 granted on 2020-06-09Low cost multi-server array architecture
#15 | 2018-11-13 β Patent 10,129,135 granted on 2018-11-13Using a neural network to determine how to direct a flow
#16 | 2018-09-04 β Patent 10,069,767 granted on 2018-09-04Method of dynamically allocating buffers for packet data received onto a networking device
#17 | 2018-08-07 β Patent 10,044,619 granted on 2018-08-07System and method for processing and forwarding transmitted information
#18 | 2018-08-02 β Patent 10,680,951 granted on 2020-06-09System and method for processing and forwarding transmitted information
#19 | 2018-07-26 β Patent 10,419,348 granted on 2019-09-17Efficient intercept of connection-based transport layer connections
#20 | 2018-07-24 β Patent 10,034,070 granted on 2018-07-24Low cost multi-server array architecture
#21 | 2018-07-24 β Patent 10,033,638 granted on 2018-07-24Executing a selected sequence of instructions depending on packet type in an exact-match flow switch
#22 | 2018-07-24 β Patent 10,032,119 granted on 2018-07-24Ordering system that employs chained ticket release bitmap block functions
#23 | 2018-06-26 β Patent 10,009,270 granted on 2018-06-26Modular and partitioned SDN switch
#24 | 2018-06-21 β Patent 10,419,406 granted on 2019-09-17Efficient forwarding of encrypted TCP retransmissions
#25 | 2018-06-12 β Patent 9,998,374 granted on 2018-06-12Method of handling SDN protocol messages in a modular and partitioned SDN switch
#26 | 2018-06-05 β Patent 9,990,307 granted on 2018-06-05Split packet transmission DMA engine
#27 | 2018-05-15 β Patent 9,971,720 granted on 2018-05-15Distributed credit FIFO link of a configurable mesh data bus
#28 | 2018-04-10 β Patent 9,940,097 granted on 2018-04-10Registered FIFO
#29 | 2018-03-27 β Patent 9,929,933 granted on 2018-03-27Loading a flow table with neural network determined information
#30 | 2018-03-06 β Patent 9,912,533 granted on 2018-03-06Serdes channel optimization
#31 | 2018-03-06 β Patent 9,912,591 granted on 2018-03-06Flow switch IC that uses flow IDs and an exact-match flow table
#32 | 2018-02-20 β Patent 9,900,090 granted on 2018-02-20Inter-packet interval prediction learning algorithm
#33 | 2018-02-20 β Patent 9,899,996 granted on 2018-02-20Recursive lookup with a hardware trie structure that has no sequential logic elements
#34 | 2018-02-13 β Patent 9,891,898 granted on 2018-02-13Low-level programming language plugin to augment high-level programming language setup of an SDN switch
#35 | 2018-02-13 β Patent 9,891,985 granted on 2018-02-13256-bit parallel parser and checksum circuit with 1-hot state information bus
#36 | 2018-02-06 β Patent 9,887,918 granted on 2018-02-06Intelligent packet data register file that stalls picoengine and retrieves data from a larger buffer
#37 | 2018-01-09 β Patent 9,866,480 granted on 2018-01-09Hash range lookup command
#38 | 2017-12-26 β Patent 9,854,072 granted on 2017-12-26Script-controlled egress packet modifier
#39 | 2017-12-14 β Patent 10,228,968 granted on 2019-03-12Network interface device that alerts a monitoring processor if configuration of a virtual NID is changed
#40 | 2017-11-14 β Patent 9,819,585 granted on 2017-11-14Making a flow ID for an exact-match flow table using a programmable reduce table circuit
#41 | 2017-10-31 β Patent 9,804,976 granted on 2017-10-31Transactional memory that performs an atomic look-up, add and lock operation
#42 | 2017-10-31 β Patent 9,807,006 granted on 2017-10-31Crossbar and an egress packet modifier in an exact-match flow switch
#43 | 2017-09-05 β Patent 9,755,911 granted on 2017-09-05On-demand generation of system entry packet counts
#44 | 2017-09-05 β Patent 9,755,910 granted on 2017-09-05Maintaining bypass packet count values
#45 | 2017-09-05 β Patent 9,755,948 granted on 2017-09-05Controlling an optical bypass switch in a data center based on a neural network output result
#46 | 2017-09-05 β Patent 9,756,152 granted on 2017-09-05Making a flow ID for an exact-match flow table using a byte-wide multiplexer circuit
#47 | 2017-09-05 β Patent 9,755,983 granted on 2017-09-05Minipacket flow control
#48 | 2017-08-08 β Patent 9,727,673 granted on 2017-08-08Simultaneous simulation of multiple blocks using efficient packet communication to emulate inter-block buses
#49 | 2017-08-08 β Patent 9,729,442 granted on 2017-08-08Method of detecting large flows within a switch fabric of an SDN switch
#50 | 2017-08-08 β Patent 9,727,513 granted on 2017-08-08Unicast packet ready command
#51 | 2017-08-08 β Patent 9,727,512 granted on 2017-08-08Identical packet multicast packet ready command
#52 | 2017-07-06 β Patent 10,031,878 granted on 2018-07-24Configurable mesh data bus in an island-based network flow processor
#53 | 2017-07-04 β Patent 9,699,084 granted on 2017-07-04Forwarding messages within a switch fabric of an SDN switch
#54 | 2017-06-13 β Patent 9,678,866 granted on 2017-06-13Transactional memory that supports put and get ring commands
#55 | 2017-06-13 β Patent 9,678,738 granted on 2017-06-13Software update methodology
#56 | 2017-05-02 β Patent 9,641,436 granted on 2017-05-02Generating a flow ID by passing packet data serially through two CCT circuits
#57 | 2017-05-02 β Patent 9,641,448 granted on 2017-05-02Packet ordering system using an atomic ticket release command of a transactional memory
#58 | 2017-04-04 β Patent 9,612,841 granted on 2017-04-04Slice-based intelligent packet data register file
#59 | 2017-03-07 β Patent 9,588,928 granted on 2017-03-07Unique packet multicast packet ready command
#60 | 2017-01-03 β Patent 9,537,801 granted on 2017-01-03Distributed packet ordering system having separate worker and output processors
#61 | 2016-12-13 β Patent 9,519,484 granted on 2016-12-13Picoengine instruction that controls an intelligent packet data register file prefetch function
#62 | 2016-11-22 β Patent 9,503,372 granted on 2016-11-22SDN protocol message handling within a modular and partitioned SDN switch
#63 | 2016-10-11 β Patent 9,467,378 granted on 2016-10-11Method of generating subflow entries in an SDN switch
#64 | 2016-08-16 β Patent 9,417,916 granted on 2016-08-16Intelligent packet data register file that prefetches data for future instruction execution
#65 | 2016-07-26 β Patent 9,401,880 granted on 2016-07-26Flow control using a local event ring in an island-based network flow processor
#66 | 2016-07-12 β Patent 9,389,908 granted on 2016-07-12Transactional memory that performs a TCAM 32-bit lookup operation
#67 | 2016-07-05 β Patent 9,385,957 granted on 2016-07-05Flow key lookup involving multiple simultaneous cam operations to identify hash values in a hash bucket
#68 | 2016-05-05 β Patent 9,804,959 granted on 2017-10-31In-flight packet processing
#69 | 2016-05-03 β Patent 9,330,041 granted on 2016-05-03Staggered island structure in an island-based network flow processor
#70 | 2016-05-03 β Patent 9,331,906 granted on 2016-05-03Compartmentalization of the user network interface to a device
#71 | 2016-04-12 β Patent 9,311,004 granted on 2016-04-12Transactional memory that performs a PMM 32-bit lookup operation
#72 | 2016-04-07 β Patent 9,705,811 granted on 2017-07-11Simultaneous queue random early detection dropping and global random early detection dropping system
#73 | 2016-04-07 β Patent 9,641,466 granted on 2017-05-02Packet storage distribution based on available memory
#74 | 2016-04-07 β Patent 9,590,926 granted on 2017-03-07Global random early detection packet dropping based on available memory
#75 | 2016-04-07 β Patent 9,485,195 granted on 2016-11-01Instantaneous random early detection packet dropping with drop precedence
#76 | 2016-03-29 β Patent 9,298,495 granted on 2016-03-29Transactional memory that performs an atomic metering command
#77 | 2016-03-24 β Patent 9,846,662 granted on 2017-12-19Chained CPP command
#78 | 2016-03-24 β Patent 10,146,468 granted on 2018-12-04Addressless merge command with data item identifier
#79 | 2016-03-08 β Patent 9,280,297 granted on 2016-03-08Transactional memory that supports a put with low priority ring command
#80 | 2016-02-25 β Patent 9,548,947 granted on 2017-01-17PPI de-allocate CPP bus command
#81 | 2016-02-25 β Patent 9,559,988 granted on 2017-01-31PPI allocation request and response for accessing a memory system
#82 | 2016-02-25 β Patent 9,699,107 granted on 2017-07-04Packet engine that uses PPI addressing
#83 | 2016-02-25 β Patent 9,413,665 granted on 2016-08-09CPP bus transaction value having a PAM/LAM selection code field
#84 | 2016-02-25 β Patent 9,703,739 granted on 2017-07-11Return available PPI credits command
#85 | 2016-02-25 β Patent 9,665,519 granted on 2017-05-30Using a credits available value in determining whether to issue a PPI allocation request to a packet engine
#86 | 2016-02-04 β Patent 9,753,725 granted on 2017-09-05Picoengine having a hash generator with remainder input S-box nonlinearizing
#87 | 2016-02-04 β Patent 9,577,832 granted on 2017-02-21Generating a hash using S-box nonlinearizing of a remainder input
#88 | 2016-01-14 β Patent 9,632,959 granted on 2017-04-25Efficient search key processing method
#89 | 2016-01-14 β Patent 9,594,706 granted on 2017-03-14Island-based network flow processor with efficient search key processing
#90 | 2016-01-14 β Patent 9,594,702 granted on 2017-03-14Multi-processor with efficient search key processing
#91 | 2016-01-14 β Patent 9,678,891 granted on 2017-06-13Efficient search key controller with standard bus interface, external memory interface, and interlaken lookaside interface
#92 | 2016-01-07 β Patent 9,258,256 granted on 2016-02-09Inverse PCP flow remapping for PFC pause frame generation
#93 | 2016-01-07 β Patent 9,515,946 granted on 2016-12-06High-speed dequeuing of buffer IDS in frame storing system
#94 | 2016-01-07 β Patent 9,270,488 granted on 2016-02-23Reordering PCP flows as they are assigned to virtual channels
#95 | 2016-01-07 β Patent 9,264,256 granted on 2016-02-16Merging PCP flows as they are assigned to a single virtual channel
#96 | 2015-12-24 β Patent 9,489,202 granted on 2016-11-08Processor having a tripwire bus port and executing a tripwire instruction
#97 | 2015-12-24 β Patent 9,495,158 granted on 2016-11-15Multi-processor system having tripwire data merging and collision detection
#98 | 2015-12-24 β Patent 9,519,482 granted on 2016-12-13Efficient conditional instruction having companion load predicate bits instruction
#99 | 2015-12-24 β Patent 9,830,153 granted on 2017-11-28Skip instruction to skip a number of instructions on a predicate
#100 | 2015-12-08 β Patent 9,208,844 granted on 2015-12-08DDR retiming circuit
Also check out Netronome Systems, Inc.'s (Santa Clara, United States) applicant profile with 134 patent applications submitted.
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