Assignee profile:

Megit Acquisition Corp.

City:

San Diego, California

Country:

United States

Published Applications:

11

Last publication date:

2014-01-23

Patent Grants:

11

Last grant date:

2014-08-19

Top Inventors for applications by Megit Acquisition Corp.

These are the the leading inventors for applications assigned to Megit Acquisition Corp.:

Recent patent applications by Megit Acquisition Corp.

Megit Acquisition Corp. based in San Diego, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:

#1 | 2014-01-23 ✅ Patent 8,809,951 granted on 2014-08-19
US20140021522A1
Electricity

Chip packages having dual DMOS devices with power management integrated circuits

#2 | 2013-11-07 ✅ Patent 8,804,360 granted on 2014-08-12
US20130292849A1
Electricity

System-in packages

#3 | 2013-05-23 ✅ Patent 8,618,580 granted on 2013-12-31
US20130127024A1
Electricity

Integrated circuit chips with fine-line metal and over-passivation metal

#4 | 2012-02-02 ✅ Patent 8,742,582 granted on 2014-06-03
US20120025378A1
Electricity

Solder interconnect on IC chip

#5 | 2011-11-03 ✅ Patent 8,692,374 granted on 2014-04-08
US20110266680A1
Electricity

Carbon nanotube circuit component structure

#6 | 2009-01-08 ✅ Patent 8,748,227 granted on 2014-06-10
US20090011542A1
Electricity

Method of fabricating chip package

#7 | 2008-06-26 ✅ Patent 8,749,021 granted on 2014-06-10
US20080150623A1
Electricity

Voltage regulator integrated with semiconductor chip

#8 | 2008-01-03 ✅ Patent 8,592,977 granted on 2013-11-26
US20080001290A1
Electricity

Integrated circuit (IC) chip and method for fabricating the same

#9 | 2007-07-19 ✅ Patent 8,742,580 granted on 2014-06-03
US20070164441A1
Electricity

Method of wire bonding over active area of a semiconductor circuit

#10 | 2006-07-06 ✅ Patent 8,723,322 granted on 2014-05-13
US20060148247A1
Chemistry; metallurgy

Method of metal sputtering for integrated circuit metal routing

#11 | 2005-01-27 ✅ Patent 8,674,507 granted on 2014-03-18
US20050017355A1
Electricity

Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer

AssigneeID:

472668 ⎘