Assignee profile:

ADVANCED SEMICONDUCTOR ENGINEERING, INC.

City:

Kaoshiung

Country:

Taiwan

Published Applications:

74

Last publication date:

2021-07-01

Patent Grants:

64

Last grant date:

2022-04-12

Top Inventors for applications by ADVANCED SEMICONDUCTOR ENGINEERING, INC.

These are the the leading inventors for applications assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC.:

Recent patent applications by ADVANCED SEMICONDUCTOR ENGINEERING, INC.

ADVANCED SEMICONDUCTOR ENGINEERING, INC. based in Kaoshiung, TW has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:

#1 | 2021-07-01 ✅ Patent 11,302,644 granted on 2022-04-12
US20210202393A1
Electricity

Semiconductor package structure and method for manufacturing the same

#2 | 2020-07-23 ✅ Patent 10,872,915 granted on 2020-12-22
US20200235153A1
Electricity

Optical package structure and method for manufacturing the same

#3 | 2020-07-23 ✅ Patent 11,024,586 granted on 2021-06-01
US20200235056A1
Electricity

Semiconductor device package and method of manufacturing the same

#4 | 2015-07-30 ✅ Patent 9,891,048 granted on 2018-02-13
US20150211852A1
Physics

Measurement equipment

#5 | 2014-01-09 ✅ Patent 8,889,488 granted on 2014-11-18
US20140011325A1
Electricity

Method for manufacturing semiconductor package

#6 | 2009-05-21 ✅ Patent 7,829,977 granted on 2010-11-09
US20090127699A1
Electricity

Low temperature co-fired ceramics substrate and semiconductor package

#7 | 2007-10-18 ✅ Patent 8,800,638 granted on 2014-08-12
US20070240848A1
Electricity

Heatsink and heatsink-positioning system

#8 | 2007-09-11 ✅ Patent 7,268,418 granted on 2007-09-11
US10747128
-

Multi-chips stacked package

#9 | 2007-08-28 ✅ Patent 7,261,828 granted on 2007-08-28
US10753318
-

Bumping process

#10 | 2007-08-28 ✅ Patent 7,262,497 granted on 2007-08-28
US10704719
-

Bumpless assembly package

#11 | 2007-08-02
US20070176278A1
Electricity

Multi-chips stacked package

#12 | 2007-08-02
US20070176269A1
Electricity

Multi-chips module package and manufacturing method thereof

#13 | 2007-07-31 ✅ Patent 7,250,677 granted on 2007-07-31
US11514827
-

Die package structure

#14 | 2007-07-26 ✅ Patent 7,446,404 granted on 2008-11-04
US20070172986A1
Electricity

Three-dimensional package and method of making the same

#15 | 2007-07-19 ✅ Patent 7,514,771 granted on 2009-04-07
US20070164406A1
Electricity

Leadless lead-frame

#16 | 2007-03-29 ✅ Patent 7,365,422 granted on 2008-04-29
US20070069345A1
Electricity

Package of leadframe with heatsinks

#17 | 2007-03-01 ✅ Patent 7,491,568 granted on 2009-02-17
US20070048899A1
Performing operations; transporting

Wafer level package and method for making the same

#18 | 2006-12-21
US20060286791A1
Electricity

Semiconductor wafer package and manufacturing method thereof

#19 | 2006-12-14 ✅ Patent 7,446,397 granted on 2008-11-04
US20060278961A1
Electricity

Leadless semiconductor package

#20 | 2006-12-05 ✅ Patent 7,144,801 granted on 2006-12-05
US10874237
-

Bumping process to increase bump height

#21 | 2006-10-17 ✅ Patent 7,122,459 granted on 2006-10-17
US10874238
-

Semiconductor wafer package and manufacturing method thereof

#22 | 2006-09-26 ✅ Patent 7,112,523 granted on 2006-09-26
US10753316
-

Bumping process

#23 | 2006-08-31
US20060192284A1
Electricity

Method of forming an encapsulation layer on a back side of a wafer

#24 | 2006-07-04 ✅ Patent 7,072,780 granted on 2006-07-04
US10745576
-

Impedance standard substrate and correction method for vector network analyzer

#25 | 2006-06-22 ✅ Patent 7,291,926 granted on 2007-11-06
US20060131718A1
Electricity

Multi-chip package structure

#26 | 2006-06-15 ✅ Patent 7,368,806 granted on 2008-05-06
US20060125113A1
Electricity

Flip chip package with anti-floating structure

#27 | 2006-05-11 ✅ Patent 7,416,919 granted on 2008-08-26
US20060099735A1
Electricity

Method for wafer level stack die placement

#28 | 2006-05-04
US20060094161A1
Electricity

Thermal enhance package and manufacturing method thereof

#29 | 2006-05-04 ✅ Patent 7,218,006 granted on 2007-05-15
US20060091560A1
Electricity

Multi-chip stack package

#30 | 2006-05-02 ✅ Patent 7,037,750 granted on 2006-05-02
US10776490
-

Method for manufacturing a package

#31 | 2006-04-27 ✅ Patent 7,235,989 granted on 2007-06-26
US20060087333A1
Physics

Electrical test device having isolation slot

#32 | 2006-04-27 ✅ Patent 7,446,409 granted on 2008-11-04
US20060087009A1
Electricity

Cavity-down multiple-chip package

#33 | 2006-04-13 ✅ Patent 7,352,056 granted on 2008-04-01
US20060076658A1
Electricity

Semiconductor package structure with microstrip antennan

#34 | 2006-04-04 ✅ Patent 7,023,079 granted on 2006-04-04
US10087432
-

Stacked semiconductor chip package

#35 | 2006-02-16 ✅ Patent 7,251,576 granted on 2007-07-31
US20060036391A1
Physics

System and method for testing CMOS image sensor

#36 | 2006-02-02 ✅ Patent 7,109,740 granted on 2006-09-19
US20060022697A1
Physics

Method for retesting semiconductor device

#37 | 2005-12-06 ✅ Patent 6,972,583 granted on 2005-12-06
US10144496
-

Method for testing electrical characteristics of bumps

#38 | 2005-10-20
US20050233571A1
Electricity

Flip chip package, semiconductor package with bumps and method for manufacturing semiconductor package with bumps

#39 | 2005-09-20 ✅ Patent 6,946,729 granted on 2005-09-20
US10417693
-

Wafer level package structure with a heat slug

#40 | 2005-09-13 ✅ Patent 6,942,478 granted on 2005-09-13
US10268161
-

Packaging mold with electrostatic discharge protection

#41 | 2005-08-18
US20050181538A1
Electricity

Semiconductor device for wire-bonding and flip-chip bonding package and manufacturing method thereof

#42 | 2005-08-16 ✅ Patent 6,929,980 granted on 2005-08-16
US10874273
-

Manufacturing method of flip chip package

#43 | 2005-08-16 ✅ Patent 6,930,389 granted on 2005-08-16
US10820829
-

Under bump metallization structure of a semiconductor wafer

#44 | 2005-08-04 ✅ Patent 7,193,282 granted on 2007-03-20
US20050168906A1
Physics

Contact sensor package

#45 | 2005-08-02 ✅ Patent 6,924,557 granted on 2005-08-02
US10327800
-

Semiconductor package

#46 | 2005-06-30 ✅ Patent 7,105,424 granted on 2006-09-12
US20050142837A1
Electricity

Method for preparing arylphosphonite antioxidant

#47 | 2005-06-30 ✅ Patent 7,235,426 granted on 2007-06-26
US20050142696A1
Electricity

Method of backside grinding a bumped wafer

#48 | 2005-06-30 ✅ Patent 7,253,529 granted on 2007-08-07
US20050140022A1
Electricity

Multi-chip package structure

#49 | 2005-06-30
US20050139997A1
Electricity

Chip assembly package

#50 | 2005-06-30 ✅ Patent 7,129,583 granted on 2006-10-31
US20050139979A1
Electricity

Multi-chip package structure

#51 | 2005-06-30 ✅ Patent 7,193,302 granted on 2007-03-20
US20050139970A1
Electricity

Leadless semiconductor package

#52 | 2005-06-21 ✅ Patent 6,908,842 granted on 2005-06-21
US10693888
-

Bumping process

#53 | 2005-06-16 ✅ Patent 7,115,484 granted on 2006-10-03
US20050130392A1
Electricity

Method of dicing a wafer

#54 | 2005-06-09 ✅ Patent 7,045,391 granted on 2006-05-16
US20050121765A1
Electricity

Multi-chips bumpless assembly package and manufacturing method thereof

#55 | 2005-05-12 ✅ Patent 7,015,571 granted on 2006-03-21
US20050098868A1
Electricity

Multi-chips module assembly package

#56 | 2005-05-05 ✅ Patent 7,326,590 granted on 2008-02-05
US20050095752A1
Electricity

Method for manufacturing ball grid array package

#57 | 2005-04-28 ✅ Patent 7,015,065 granted on 2006-03-21
US20050090043A1
Electricity

Manufacturing method of ball grid array package

#58 | 2005-04-28 ✅ Patent 7,144,239 granted on 2006-12-05
US20050089594A1
Performing operations; transporting

Molding apparatus with a molding flowability sensor for packaging semiconductor device

#59 | 2005-04-21 ✅ Patent 7,187,070 granted on 2007-03-06
US20050082656A1
Electricity

Stacked package module

#60 | 2005-04-12 ✅ Patent 6,879,031 granted on 2005-04-12
US10747189
-

Multi-chips package

#61 | 2005-04-12 ✅ Patent 6,878,963 granted on 2005-04-12
US10287336
-

Device for testing electrical characteristics of chips

#62 | 2005-04-07 ✅ Patent 7,102,241 granted on 2006-09-05
US20050073032A1
Electricity

Leadless semiconductor package

#63 | 2005-03-31
US20050067720A1
Electricity

Method of forming an encapsulation layer on a back side of a wafer

#64 | 2005-03-24 ✅ Patent 7,049,689 granted on 2006-05-23
US20050062142A1
Physics

Chip on glass package

#65 | 2005-03-17
US20050056933A1
Electricity

Bumped wafer with adhesive layer encompassing bumps and manufacturing method thereof

#66 | 2005-03-03 ✅ Patent 7,291,924 granted on 2007-11-06
US20050046040A1
Electricity

Flip chip stacked package

#67 | 2005-03-03 ✅ Patent 7,145,222 granted on 2006-12-05
US20050046008A1
Electricity

Leadless semiconductor package

#68 | 2005-03-01 ✅ Patent 6,861,761 granted on 2005-03-01
US10697111
-

Multi-chip stack flip-chip package

#69 | 2005-02-24 ✅ Patent 7,033,914 granted on 2006-04-25
US20050042844A1
Performing operations; transporting

Method of making a package structure by dicing a wafer from the backside surface thereof

#70 | 2005-02-17 ✅ Patent 7,429,342 granted on 2008-09-30
US20050037178A1
Performing operations; transporting

Method for cleaning and regenerating a mold

#71 | 2005-02-15 ✅ Patent 6,856,027 granted on 2005-02-15
US10820826
-

Multi-chips stacked package

#72 | 2005-02-03 ✅ Patent 7,221,041 granted on 2007-05-22
US20050023667A1
Electricity

Multi-chips module package and manufacturing method thereof

#73 | 2005-01-18 ✅ Patent 6,844,617 granted on 2005-01-18
US10292303
-

Packaging mold with electrostatic discharge protection

#74 | 2005-01-13 ✅ Patent 7,223,683 granted on 2007-05-29
US20050009317A1
Electricity

Wafer level bumping process

Also check out ADVANCED SEMICONDUCTOR ENGINEERING, INC.'s (Kaoshiung, Taiwan) applicant profile with 2 patent applications submitted.

AssigneeID:

51322 ⎘