MACOM CONNECTIVITY SOLUTIONS, LLC

Analog delay based fractionally spaced n-tap feed-forward equalizer for wireline and optical transmitters

Multiple datastreams processing by fragment-based timeslicing

High speed buffering for time-interleaved ADCS with reduced ISI and increased voltage gain

Power optimization mechanisms for framers by serializing frame alignment processes for multiple lanes

Power optimization mechanisms for framers by using serial comparison in frame alignment process

Power optimization mechanisms for framers by selectively deactivating frame alignment process

Concatenates of an E8 lattice with binary and non binary codes

Mitigating interaction between adaptive equalization and timing recovery

Resolving interaction between channel estimation and timing recovery

Timing recovery with adaptive channel response estimation

High speed serializer using quadrature clocks

Data managment for cache memory

Flexible and robust power grid connectivity

High speed add-compare-select for Viterbi decoder

Systems and methods facilitating reduced latency via stashing in system on chips

Split loop timing recovery

Main memory prefetch operation and multiple prefetch operation

System and method for monitoring encoded signals in a network

Duplex transmission over reduced pairs of twinax cables

Multi-rate transmissions over twinax cables

Times-sliced design segmentation

Allocation of load instruction(s) to a queue buffer in a processor system based on prediction of an instruction pipeline hazard

Multiple datastreams processing by fragment-based timeslicing