HYNIX SEMICONDUCTOR INC.

Trimming of operative parameters in electronic devices based on corrections mappings

Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same

Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same

Semiconductor package having substrate for high speed semiconductor package

Vertical transistor and method for forming the same

Semiconductor package with a reduced volume and thickness and capable of high speed operation and method for fabricating the same

Phase change memory device to prevent thermal cross-talk and method for manufacturing the same

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same

Phase change memory device having a bent heater and method for manufacturing the same

Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same

Semiconductor device having vertical pillar transistors and method for manufacturing the same

Semiconductor device for preventing the leaning of storage nodes and method for manufacturing the same

Stacked semiconductor package

Semiconductor device and method of manufacturing the same

Metal line of semiconductor device having a diffusion barrier with an amorphous TaBN layer and method for forming the same

Electrostatic discharge protection circuit having a reduced size and enhanced discharge

Apparatus for detecting pattern alignment error

Sense amplifier for controlling flip error and driving method thereof

Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same

Integrated circuit with embedded RFID

Phase change memory device capable of increasing sensing margin and method for manufacturing the same

Impedance calibration circuit, semiconductor memory device with the impedance calibration circuit and layout method of internal resistance in the impedance calibration circuit

Phase change memory device in which a phase change layer is stably formed and prevented from lifting and method for manufacturing the same

Semiconductor device and method for forming the same

Semiconductor memory testing device and method of testing semiconductor using the same

Trimming of operative parameters in electronic devices based on corrections mappings

Semiconductor package having a stacked wafer level package and method for fabricating the same

Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof

Zero capacitor RAM with reliable drain voltage application and method for manufacturing the same

Stacked semiconductor package and method for manufacturing the same

Semiconductor device and method of fabricating the same

Delay locked loop apparatus

Forming a buried word line and connection pad for memory apparatus

Method for manufacturing semiconductor device having buried gate

Phase change memory device having dielectric layer for isolating contact structure formed by growth, semiconductor device having the same, and methods for manufacturing the devices

Semiconductor device and semiconductor package having the same

Phase change RAM device and method for fabricating the same

Lightweight and compact through-silicon via stack package with excellent electrical connections and method for manufacturing the same

Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers

Method for manufacturing semiconductor device having porous low dielectric constant layer formed for insulation between metal lines

Stacked semiconductor package and method for manufacturing the same

Flash memory device and mask for fabricating the same

Manufacturing method of transistor structure having a recessed channel

Semiconductor device having asymmetric bulb-type recess gate and method for manufacturing the same

Circuit providing compensated power for sense amplifier and driving method thereof

Standardization of assist pattern inserted into outermost pattern for enhancing depth of focus margin

Method for forming semiconductor device

Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same

Recessed gate electrode MOS transistor and method for fabricating the same

Circuit board having conductive shield member and semiconductor package using the same

Warpage resistant semiconductor package and method for manufacturing the same

Sense amplifier and driving method thereof, and semiconductor memory device having the sense amplifier

Semiconductor memory apparatus

Semiconductor package with improved size, reliability, warpage prevention, and heat dissipation and method for manufacturing the same

Dual gate of semiconductor device capable of forming a layer doped in high concentration over a recessed portion of substrate for forming dual gate with recess channel structure and method for manufacturing the same

Semiconductor device and method of fabricating the same

Semiconductor memory device

Semiconductor device having multiple-layer hard mask with opposite stresses and method for fabricating the same

Phase change memory device having decentralized driving units

Buffer control circuit of memory device

Square pillar-shaped switching element for memory device and method of manufacturing the same

Method for optical proximity correction

Method for manufacturing semiconductor device with improved short channel effect of a PMOS and stabilized current of a NMOS

Semiconductor memory device

Semiconductor device and semiconductor package having the same

Method for efficiently driving a phase change memory device

Semiconductor device with contact stabilization between contact plugs and BIT lines and method for manufacturing the same

Phase change memory device resistant to stack pattern collapse and a method for manufacturing the same

Phase change memory device resistant to stack pattern collapse and a method for manufacturing the same

Semiconductor device for reducing interference between adjoining gates and method for manufacturing the same

Clock divider and clock dividing method for a DLL circuit

Semiconductor package and method for manufacturing the same for decreasing number of processes

NAND flash memory device

Semiconductor package adapted for high-speed data processing and damage prevention of chips packaged therein and method for fabricating the same

1-transistor type DRAM cell, DRAM device and DRAM comprising thereof and driving method thereof and manufacturing method thereof

Multi-layer metal wiring of semiconductor device preventing mutual metal diffusion between metal wirings and method for forming the same

Semiconductor device having multi-channel and method of fabricating the same

Semiconductor device having bulb-shaped recess gate and method for fabricating the same

Anti-fuse repair control circuit and semiconductor device including DRAM having the same

Sense amplifier control circuit

Semiconductor memory apparatus having decreased leakage current

Phase change memory device