Fremont, California
United States
22
2016-05-19
22
2016-09-13
These are the the leading inventors for applications assigned to Aplus Flash Technology, Inc.:
Aplus Flash Technology, Inc. based in Fremont, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
NAND array architecture for multiple simultaneous program and read
#2 | 2016-04-21 ✅ Patent 9,437,306 granted on 2016-09-06NAND array architecture for multiple simutaneous program and read
#3 | 2016-03-31 ✅ Patent 9,666,286 granted on 2017-05-30Self-timed SLC NAND pipeline and concurrent program without verification
#4 | 2016-02-18 ✅ Patent 9,443,579 granted on 2016-09-13VSL-based VT-compensation and analog program scheme for NAND array without CSL
#5 | 2014-11-27 ✅ Patent 9,001,545 granted on 2015-04-07NOR-based BCAM/TCAM cell and array with NAND scalability
#6 | 2014-11-27 ✅ Patent 9,183,940 granted on 2015-11-10Low disturbance, power-consumption, and latency in NAND read and program-verify operations
#7 | 2014-05-01 ✅ Patent 8,976,588 granted on 2015-03-10NVSRAM cells with voltage flash charger
#8 | 2014-05-01 ✅ Patent 8,971,113 granted on 2015-03-03Pseudo-8T NVSRAM cell with a charge-follower
#9 | 2014-04-17 ✅ Patent 9,001,583 granted on 2015-04-07On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation
#10 | 2014-03-27 ✅ Patent 8,964,470 granted on 2015-02-24Method and architecture for improving defect detectability, coupling area, and flexibility of NVSRAM cells and arrays
#11 | 2013-10-24 ✅ Patent 9,087,595 granted on 2015-07-21Shielding 2-cycle half-page read and program schemes for advanced NAND flash design
#12 | 2013-10-17 ✅ Patent 9,171,627 granted on 2015-10-27Non-boosting program inhibit scheme in NAND design
#13 | 2013-05-23 ✅ Patent 9,019,764 granted on 2015-04-28Low-voltage page buffer to be used in NVM design
#14 | 2012-07-12 ✅ Patent 8,917,551 granted on 2014-12-23Flexible 2T-based fuzzy and certain matching arrays
#15 | 2012-06-21 ✅ Patent 8,634,241 granted on 2014-01-21Universal timing waveforms sets to improve random access read and write speed of memories
#16 | 2012-04-12 ✅ Patent 8,837,221 granted on 2014-09-16Write bias condition for 2T-string NOR flash cell
#17 | 2012-03-22 ✅ Patent 9,063,849 granted on 2015-06-23Different types of memory integrated in one chip by using a novel protocol
#18 | 2012-03-22 ✅ Patent 8,809,148 granted on 2014-08-19EEPROM-based, data-oriented combo NVM design
#19 | 2012-03-15 ✅ Patent 8,933,500 granted on 2015-01-13EEPROM-based, data-oriented combo NVM design
#20 | 2011-09-29 ✅ Patent 8,634,254 granted on 2014-01-21Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reduction
#21 | 2011-03-24 ✅ Patent 8,996,785 granted on 2015-03-31NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface
#22 | 2011-03-24 ✅ Patent 8,775,719 granted on 2014-07-08NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface
Also check out Aplus Flash Technology, Inc's (Fremont, United States) applicant profile with 7 patent applications submitted.
83443 ⎘