Sunnyvale, California
United States
55
2015-11-26
54
2016-03-01
These are the the leading inventors for applications assigned to Syntest Technologies, Inc.:
Syntest Technologies, Inc. based in Sunnyvale, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
#2 | 2015-11-26 ✅ Patent 9,696,377 granted on 2017-07-04Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
#3 | 2015-11-05 ✅ Patent 9,316,688 granted on 2016-04-19Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
#4 | 2014-11-20 ✅ Patent 9,121,902 granted on 2015-09-01Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
#5 | 2014-08-07 ✅ Patent 9,091,730 granted on 2015-07-28Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
#6 | 2014-05-29 ✅ Patent 9,110,139 granted on 2015-08-18Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
#7 | 2014-05-22METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION
#8 | 2014-03-20 ✅ Patent 8,769,359 granted on 2014-07-01Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
#9 | 2014-03-13 ✅ Patent 9,046,572 granted on 2015-06-02Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
#10 | 2014-03-13 ✅ Patent 9,057,763 granted on 2015-06-16Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
#11 | 2013-11-14 ✅ Patent 8,775,985 granted on 2014-07-08Computer-aided design system to automate scan synthesis at register-transfer level
#12 | 2013-10-10 ✅ Patent 9,026,875 granted on 2015-05-05Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
#13 | 2013-02-07 ✅ Patent 8,949,299 granted on 2015-02-03Method and apparatus for hybrid ring generator design
#14 | 2012-12-27 ✅ Patent 8,667,451 granted on 2014-03-04Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
#15 | 2012-10-18 ✅ Patent 8,335,954 granted on 2012-12-18Method and apparatus for low-pin-count scan compression
#16 | 2012-09-27 ✅ Patent 8,543,950 granted on 2013-09-24Computer-aided design system to automate scan synthesis at register-transfer level
#17 | 2012-06-28 ✅ Patent 8,458,544 granted on 2013-06-04Multiple-capture DFT system to reduce peak capture power during self-test or scan test
#18 | 2012-05-03 ✅ Patent 8,522,096 granted on 2013-08-27Method and apparatus for testing 3D integrated circuits
#19 | 2011-10-20 ✅ Patent 8,230,282 granted on 2012-07-24Method and apparatus for low-pin-count scan compression
#20 | 2011-08-11 ✅ Patent 8,219,945 granted on 2012-07-10Computer-aided design system to automate scan synthesis at register-transfer level
#21 | 2011-05-17 ✅ Patent 7,945,833 granted on 2011-05-17Method and apparatus for pipelined scan compression
#22 | 2011-04-12 ✅ Patent 7,925,947 granted on 2011-04-12X-canceling multiple-input signature register (MISR) for compacting output responses with unknowns
#23 | 2011-02-24 ✅ Patent 7,996,741 granted on 2011-08-09Method and apparatus for low-pin-count scan compression
#24 | 2010-11-11 ✅ Patent 8,091,002 granted on 2012-01-03Multiple-capture DFT system to reduce peak capture power during self-test or scan test
#25 | 2010-08-26 ✅ Patent 7,945,830 granted on 2011-05-17Method and apparatus for unifying self-test with scan-test during prototype debug and production test
#26 | 2010-08-17 ✅ Patent 7,779,322 granted on 2010-08-17Compacting test responses using X-driven compactor
#27 | 2009-12-10 ✅ Patent 7,783,940 granted on 2010-08-24Apparatus for redundancy reconfiguration of faculty memories
#28 | 2009-09-17 ✅ Patent 7,721,173 granted on 2010-05-18Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
#29 | 2009-06-23 ✅ Patent 7,552,373 granted on 2009-06-23Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
#30 | 2009-05-21 ✅ Patent 7,779,323 granted on 2010-08-17Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
#31 | 2009-03-12 ✅ Patent 7,904,773 granted on 2011-03-08Multiple-capture DFT system for scan-based integrated circuits
#32 | 2009-02-05 ✅ Patent 7,747,920 granted on 2010-06-29Method and apparatus for unifying self-test with scan-test during prototype debug and production test
#33 | 2008-11-06 ✅ Patent 7,721,172 granted on 2010-05-18Method and apparatus for broadcasting test patterns in a scan-based integrated circuit
#34 | 2008-10-28 ✅ Patent 7,444,567 granted on 2008-10-28Method and apparatus for unifying self-test with scan-test during prototype debug and production test
#35 | 2008-08-12 ✅ Patent 7,412,672 granted on 2008-08-12Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
#36 | 2008-06-05 ✅ Patent 7,904,857 granted on 2011-03-08Computer-aided design system to automate scan synthesis at register-transfer level
#37 | 2007-11-01 ✅ Patent 7,434,126 granted on 2008-10-07Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
#38 | 2007-08-21 ✅ Patent 7,260,756 granted on 2007-08-21Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
#39 | 2007-07-19 ✅ Patent 7,284,175 granted on 2007-10-16Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
#40 | 2007-04-24 ✅ Patent 7,210,082 granted on 2007-04-24Method for performing ATPG and fault simulation in a scan-based integrated circuit
#41 | 2007-03-13 ✅ Patent 7,191,373 granted on 2007-03-13Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
#42 | 2006-10-26 ✅ Patent 7,412,637 granted on 2008-08-12Method and apparatus for broadcasting test patterns in a scan based integrated circuit
#43 | 2006-07-13 ✅ Patent 7,735,049 granted on 2010-06-08Mask network design for scan-based integrated circuits
#44 | 2006-06-06 ✅ Patent 7,058,869 granted on 2006-06-06Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
#45 | 2006-03-23 ✅ Patent 7,590,905 granted on 2009-09-15Method and apparatus for pipelined scan compression
#46 | 2006-03-16 ✅ Patent 7,228,479 granted on 2007-06-05IEEE Std. 1149.4 compatible analog BIST methodology
#47 | 2006-02-28 ✅ Patent 7,007,213 granted on 2006-02-28Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
#48 | 2005-12-01 ✅ Patent 7,231,570 granted on 2007-06-12Method and apparatus for multi-level scan compression
#49 | 2005-11-24 ✅ Patent 7,124,342 granted on 2006-10-17Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
#50 | 2005-10-20 ✅ Patent 7,451,371 granted on 2008-11-11Multiple-capture DFT system for scan-based integrated circuits
#51 | 2005-10-18 ✅ Patent 6,957,403 granted on 2005-10-18Computer-aided design system to automate scan synthesis at register-transfer level
#52 | 2005-10-13 ✅ Patent 7,331,032 granted on 2008-02-12Computer-aided design system to automate scan synthesis at register-transfer level
#53 | 2005-10-11 ✅ Patent 6,954,887 granted on 2005-10-11Multiple-capture DFT system for scan-based integrated circuits
#54 | 2005-03-17 ✅ Patent 7,032,148 granted on 2006-04-18Mask network design for scan-based integrated circuits
#55 | 2005-03-10 ✅ Patent 7,512,851 granted on 2009-03-31Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
Also check out Syntest Technologies, Inc.'s (Sunnyvale, United States) applicant profile with 12 patent applications submitted.
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