ClassID:

171800

G01R31/2898 - CPC Classification

Classification description:

Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of integrated circuits [IC] Sample preparation, e.g. removing encapsulation, etching

Recent Application in this class:
#1
20250199061
2025-06-19

Method of Identifying Vulnerable Regions in an Integrated Circuit

#2
20230375616
2023-11-23

Methods and structures for semiconductor device testing

#3
20230273256
2023-08-31

CONTRAST-ENHANCING STAINING SYSTEM AND METHOD AND IMAGING METHODS AND SYSTEMS RELATED THERETO

#4
20230138247
2023-05-04

Method of identifying vulnerable regions in an integrated circuit

#5
20220155367
2022-05-19

Method of preparing a semiconductor specimen for failure analysis

#6
20220128627
2022-04-28

Die extraction method

#7
20220005669
2022-01-06

Ion beam delayering system and method, topographically enhanced delayered sample produced thereby, and imaging methods and systems related thereto

#8
20200211924
2020-07-02

Thermal interface formed by condensate

#9
20200057105
2020-02-20

Wafer surface test preprocessing device and wafer surface test apparatus having the same

#10
20190005174
2019-01-03

Methods and apparatus for performing timing driven hardware emulation

#11
20180252747
2018-09-06

Integrated self-coining probe

#12
20180231605
2018-08-16

Configurable Vertical Integration

#13
20180180666
2018-06-28

Integrated circuit device testing in an inert gas

#14
20180025952
2018-01-25

Reverse decoration for defect detection amplification

#15
20180017614
2018-01-18

Configurable Vertical Integration

#16
20160282643
2016-09-29

Rolling apparatus and rolling method

#17
20160187417
2016-06-30

Testing method

#18
20160003869
2016-01-07

Test carrier for mounting and testing an electronic device

#19
20150260784
2015-09-17

Multidimensional structural access

#20
20150130500
2015-05-14

Configurable vertical integration

#21
20150044788
2015-02-12

Test apparatus and test method

#22
20140361806
2014-12-11

Configurable vertical integration

#23
20140167808
2014-06-19

Interconnect solder bumps for die testing

#24
20130330846
2013-12-12

TEST VEHICLES FOR ENCAPSULATED SEMICONDUCTOR DEVICE PACKAGES

#25
20130273674
2013-10-17

Apparatus and method for endpoint detection during electronic sample preparation

#26
20130273671
2013-10-17

Apparatus and method for endpoint detection during electronic sample preparation

#27
20130271169
2013-10-17

Apparatus and method for electronic sample preparation

#28
20130193995
2013-08-01

Methods and devices for stressing an integrated circuit

#29
20130049782
2013-02-28

Method for cleaning a contact pad of a microstructure and corresponding cantilever contact probe and probe testing head

#30
20110139368
2011-06-16

APPARATUS AND SYSTEMS FOR INTEGRATED CIRCUIT DIAGNOSIS

#31
20100140616
2010-06-10

Electronic device and method for manufacturing the same

#32
20080231303
2008-09-25

SEMICONDUCTOR DEVICE FOR ELECTRICAL CONTACTING SEMICONDUCTOR DEVICES

#33
20080206960
2008-08-28

REWORKABLE CHIP STACK

#34
20080157077
2008-07-03

Integrated circuit and methods of measurement and preparation of measurement structure

#35
20080142482
2008-06-19

Multipurpose decapsulation holder and method for a ball grid array package

#36
20080128086
2008-06-05

Backside unlayering of MOSFET devices for electrical and physical characterization

#37
20080054920
2008-03-06

Method For Evaluating Soi Wafer

#38
20080009140
2008-01-10

Electron induced chemical etching for device level diagnosis

#39
20070222471
2007-09-27

Front and back side dynamically-biased photon emission microscopy

#40
20070164236
2007-07-19

Method for retrieving signal from circuit

#41
20070125958
2007-06-07

Stage assembly, particle-optical apparatus comprising such a stage assembly, and method of treating a sample in such an apparatus

#42
20070046314
2007-03-01

Process for testing IC wafer

#43
20060267009
2006-11-30

Method for local wafer thinning and reinforcement

#44
20060139049
2006-06-29

Planar view TEM sample preparation from circuit layer structures

#45
20060119375
2006-06-08

Apparatus and method for testing semiconductor chip

#46
20060061374
2006-03-23

Inspection method and inspection equipment

#47
20060031068
2006-02-09

Analysis method

#48
20060030160
2006-02-09

Backside unlayering of MOSFET devices for electrical and physical characterization

#49
20050283335
2005-12-22

Methods of measurement and preparation of measurement structure of integrated circuit

#50
20050167400
2005-08-04

System and method for decapsulating an encapsulated object

#51
20050151549
2005-07-14

Probe method, prober, and electrode reducing/plasma-etching processing mechanism

#52
20050148157
2005-07-07

Method of processing backside unlayering of MOSFET devices for electrical and physical characterization including a collimated ion plasma

#53
20050136563
2005-06-23

Backside failure analysis of integrated circuits

#54
20050073333
2005-04-07

Specific site backside underlaying and micromasking method for electrical characterization of semiconductor devices

#55
20050064682
2005-03-24

Failure analysis methods and systems