171823 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits Arrangements for setting the Unit Under Test [UUT] in a test mode
VOLTAGE DROOP MITIGATION DURING AUTOMOTIVE ELECTRONICS BUILT IN SELF TEST
#2RESET TEST SYSTEM AND SYSTEM-ON-CHIP INCLUDING THE SAME
#3NEURAL PROCESSING UNIT PERFORMING TEST FOR DETECTING FAILURE
#4DEVICE TESTING SYSTEM AND DEVICE TESTING METHOD
#5Test time reduction in circuits with redundancy flip-flops
#6RESET FOR SCAN MODE EXIT FOR DEVICES WITH POWER-ON RESET GENERATION CIRCUITRY
#7PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT
#8NPU CAPABLE OF BEING TESTED DURING RUNTIME
#9TEST MODE CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS AND SYSTEM, AND METHOD THEREOF
#10SOLID STATE ESD SIC SIMULATOR
#11Method for checking DFT circuit, test platform, storage medium and test system
#12Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same
#13Methods and systems for identifying flaws and bugs in integrated circuits, for example, microprocessors
#14Memory temperature controlling method and memory temperature controlling system
#15Reduced signaling interface method and apparatus
#16Solid state ESD SiC simulator
#17SYSTEMS AND DEVICES FOR INTELLIGENT INTEGRATED TESTING
#18Systems and methods for fault detection and reporting through serial interface transceivers
#19System and method for facilitating built-in self-test of system-on-chips
#20System and method of testing single DUT through multiple cores in parallel
#21System and method for parallel testing of electronic device
#22Single pin DFT architecture for USBPD ICs
#23Functional tester for printed circuit boards, and associated systems and methods
#24Methods and systems for single-event upset fault injection testing
#25System capable of detecting failure of component of system and method thereof
#26Method and apparatus for debugging integrated circuit systems using scan chain
#27Implementing a JTAG device chain in multi-die integrated circuit
#28Flexible test systems and methods
#29Scan test device and scan test method
#30Measurement of internal wire delay
#31Extended JTAG controller and method for functional reset using the extended JTAG controller
#32Integrated circuit with reduced signaling interface
#33Implementing a JTAG device chain in multi-die integrated circuit
#34Systems and methods for fault detection and reporting through serial interface transceivers
#35Controller accessible test access port controls
#36Integrated circuit with self-test circuit, method for operating an integrated circuit with self-test circuit, multi-core processor device and method for operating a multi-core processor device
#37Secure scan entry
#38Method and apparatus for testing artificial intelligence chip, device and storage medium
#39Self-test of an asynchronous circuit
#40Self test for safety logic
#41Debugging solution for multi-core processors
#42Digital circuit robustness verification method and system
#43Reduced signaling interface circuit
#44Electrical circuit for testing primary internal signals of an ASIC
#45Self-calibrating deskew fixture
#46Data channel optimization with smart black box algorithms
#47System and method for parallel testing of electronic device
#48Test instruments and methods for compensating IQ imbalance
#49Time interleaved scan system
#50Semiconductor apparatus
#51Two pin scan interface for low pin count devices
#52Device and methods for reducing peak noise and peak power consumption in semiconductor devices under test
#53Functional tester for printed circuit boards, and associated systems and methods
#54Test instruments and methods for compensating IQ imbalance
#55Measuring system with antenna alignment
#56Entering home state after soft reset signal after address match
#57System and method for testing and configuration of an FPGA
#58Display device and method of inspecting display device
#59Semiconductor apparatus
#60Systems and methods for bypass testing
#61Error rate meter included in a semiconductor die
#62Method for controlling wireless device under test using non-link testing resources
#63Dynamic probe, dynamic measurement system and method for probing a dynamic data signal
#64CONTROLLING A TRANSITION BETWEEN A FUNCTIONAL MODE AND A TEST MODE
#65TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs
#66Self-test of an asynchronous circuit
#67Product performance test binning
#68Test circuit capable of measuring PLL clock signal in ATPG mode
#69System and method for testing and configuration of an FPGA
#70Test mode control circuit
#71Self test for safety logic
#72Device, system and method for providing on-chip test/debug functionality
#73Scan data control apparatus and electronic system having the same
#74Memory device
#75Address/instruction registers, target domain interfaces, control information controlling all domains
#76Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains
#77Testing circuit board with self-detection function and self-detection method thereof
#78Testing a board assembly using test cards
#79System Test Mode For Electricity Meter In A Metering Network
#80Semiconductor device method relating to latch circuit testing
#81Adjusting latency in a scan cell
#82Adjusting latency in a scan cell
#83Taps with TO-T2, T4 classes with, without topology selection logic
#84Multi-bit data flip-flop with scan initialization
#85Reconfigurable test access port with finite state machine control
#86Apparatus and method for measuring relative frequency response of audio device microphones
#87Integrated circuit with auxiliary electrical power supply pins
#88Method for managing the operation of a test mode of a logic component with restoration of the pre-test state
#89Semiconductor apparatus
#90Multi-chassis test device and test signal transmission apparatus of the same
#91Test mode control circuit
#92Debugging method executed via scan chain for scan test and related circuitry system
#93Integrated circuit with low power scan system
#94Granular dynamic test systems and methods
#95Independent test partition clock coordination across multiple test partitions
#96Dynamic independent test partition clock
#97Scan system interface (SSI) module
#98Method and system for dynamic standard test access (DSTA) for a logic block reuse
#99Test partition external input/output interface control for test partitions in a semiconductor
#100Testing electronic devices
#101High speed interconnect circuit test method and apparatus
#102Addressable tap domain selection circuit with instruction and linking circuits
#103TCK, TMS(C) clock, gating circuitry providing selection and deselection outputs
#104Taps of different scan classes with, without topology selection logic
#105Security system and methods for integrated devices
#106Semiconductor devices, semiconductor systems including the same, methods of testing the same
#107Test mode circuit and semiconductor device including the same
#108Semiconductor device, physical quantity sensor, electronic apparatus, and moving object
#109Controlling a test run on a device under test without directly controlling the test equipment within a vendor test platform testing the device under test
#110Test setting circuit, semiconductor device, and test setting method
#111Secure low voltage testing
#112Semiconductor device with test mode circuit
#113Semiconductor apparatus
#114Monitoring circuit of semiconductor device to monitor a read-period signal during activation of a boot-up enable signal
#115Test mode entry interlock
#116Method for testing integrated circuit and integrated circuit configured to facilitate performing such a method
#117Integrated circuit
#118Method for performing built-in self-tests
#119Built-in self test system, system on a chip and method for controlling built-in self tests
#120Method and apparatus for testing surface mounted devices
#121Semiconductor device
#122Reconfigurable circuit and decoder therefor
#123Testing an integrated circuit
#124Semiconductor device
#125Semiconductor apparatus with boundary scan test circuit
#126Semiconductor memory devices and methods of testing open failures thereof
#127Packet switch based logic replication
#128Semiconductor device with test mode circuit
#129Power up detecting system
#130Semiconductor integrated circuit and test control method thereof
#131Product performance test binning
#132METHODS FOR INVOKING TESTING USING REVERSIBLE CONNECTORS
#133CONNECTORS FOR INVOKING AND SUPPORTING DEVICE TESTING
#134INVOKING AND SUPPORTING DEVICE TESTING THROUGH AUDIO CONNECTORS
#135Advanced/enhanced protocol circuitry connected to TCK, TMS, and topology circuitry
#136Voltage supply droop detector
#137Address and instruction controller with TCK, TMS, address match inputs
#138Integrated device test circuits and methods
#139SEMICONDUCTOR DEVICE AND METHOD FOR TESTING SAME
#140CIRCUIT APPARATUS
#141TEST MODE SETTING CIRCUIT
#142Method of protecting a test circuit
#143No pin test mode
#144Integrated circuit arrangement for test inputs
#145Semiconductor device for performing test operation and method thereof
#146System for performing the test of digital circuits
#147Instruction register delay select outputs to clock delay circuitry
#148Inverter and TMS clocked flip-flop pairs between TCK and reset
#149Packet switch based logic replication
#150Reduced signaling interface method and apparatus
#151Test pin gating for dynamic optimization
#152Test mode signal generating device
#153Test mode for multi-chip integrated circuit packages
#154Probing structure for evaluation of slow slew-rate square wave signals in low power circuits
#155Semiconductor device capable of verifying reliability
#156Timer unit, system, computer program product and method for testing a logic circuit
#157Clock delay circuits and multiplexer connected to boundary scan circuitry
#158Reduced signaling interface method and apparatus
#159SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME
#160Automatic scan format selection based on scan topology selection
#161Selecting a scan topology
#162Series equivalent scans across multiple scan topologies
#163Ascertaining configuration by storing data signals in a topology register
#164Dynamic broadcast of configuration loads supporting multiple transfer formats
#165Alternate Signaling Mechanism Using Clock and Data
#166Test mode enable circuit
#167Test circuit for performing multiple test modes
#168Integrated circuit and method for operating
#169SEMICONDUCTOR DEVICE AND TEST MODE CONTROL CIRCUIT
#170Local and global address compare with tap interface TDI/TDO lead
#171Propagation test strobe circuitry with boundary scan circuitry
#172Semiconductor integrated circuit and debug mode determination method
#173Circuit and data carrier with radio frequency interface
#174Device and method for testing integrated circuit dice in an integrated circuit module
#175Test mode control circuit
#176Test circuit for supporting concurrent test mode in a semiconductor memory
#177Test circuit for performing multiple test modes
#178Method of controlling a test mode of a circuit
#179Synchronous semiconductor device, and inspection system and method for the same
#180Semiconductor device for performing mount test in response to internal test mode signals
#181Semiconductor package capable of performing various tests and method of testing the same
#182Tri-level test mode terminal in limited terminal environment
#183Semiconductor device with multipurpose pad
#184Electronic device having an interface supported testing mode
#185Test mode for multi-chip integrated circuit packages
#186Propagation test strobe circuitry with boundary scan circuitry
#187Voltage drop measurement circuit
#188Semiconductor device, semiconductor device testing method, and probe card
#189Method and apparatus for entering special mode in integrated circuit
#190Semiconductor apparatus and test execution method for semiconductor apparatus
#191Test mode for pin-limited devices
#192Test access architecture and method of testing a module in an electronic circuit
#193Testing circuit and testing method for semiconductor device and semiconductor chip
#194Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same
#195Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same
#196Operation mode setting circuit, LSI having operation mode setting circuit, and operation mode setting method
#197Integrated circuit with integrated circuit section to aid in testing
#198Test mode control circuit
#199Design data structure for semiconductor integrated circuit and apparatus and method for designing the same
#200Electronic device having an interface supported testing mode
#201Device and method for testing integrated circuit dice in an integrated circuit module
#202AC propagation testing preventing sampling test data at Capture-DR state
#203Scan-based self-test structure and method using weighted scan-enable signals
#204Semiconductor integrated circuit device with a test circuit that measures a period to select a test mode
#205Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same
#206Enabling special modes within a digital device
#207Addressable tap domain selection circuit with TDI/TDO external terminal
#208Method for testing semiconductor chips using check bits
#209Method for testing semiconductor chips by means of bit masks
#210Shared bond pad for testing a memory within a packaged semiconductor device
#211Single pin multilevel integrated circuit test interface
#212Generation of test mode signals in memory device with minimized wiring
#213Processor condition sensing circuits, systems and methods
#214Semiconductor integrated circuit device
#215Method and system for ensuring the assertion order of signals in a chip independent of physical layout
#216Electronic circuit with asynchronously operating components
#217Interface circuit for a single logic input pin of an electronic system
#218Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit
#219Test terminal negation circuit for protecting data integrity
#220Integrated circuit
#221Operation mode setting circuit
#222Test switching circuit for a high speed data interface
#223Integrated circuit device with multiple chips in one package
#224Semiconductor integrated circuit device
#225Semiconductor device and method for testing the same
#226Test mode circuit of semiconductor device
#227Circuit for controlling internal supply voltage driver
#228Synchronous semiconductor device, and inspection system and method for the same
#229Dual mode analog differential and CMOS logic circuit
#230Semiconductor device and method of inspecting the same
#231Integration type input circuit and method of testing it
#232GaN HEMT device for irradiation damage detection and detection and manufacturing method therefor
#233Smart storage of shutdown LBIST status
#234United states test controller for system-on-chip validation
#235Clock control system for scan chains
#236Constrained pseudorandom test pattern for in-system logic built-in self-test
#237Increase data transfer throughput by enabling dynamic JTAG test mode entry and sharing of all JTAG pins
#238Apparatus and method for measuring relative frequency response of audio device microphones
#239System and methods for debug connectivity discovery
#240Bandgap with thermal drift correction
#241Automatic and on-demand testing of non-volatile storage devices
#242Method and system for gathering signal states for debugging a circuit