SECURE SCAN TESTING OF INTEGRATED CIRCUITS

SYSTEMS AND METHODS FOR TESTING INTEGRATED CIRCUITS INDEPENDENT OF CHIP PACKAGE CONFIGURATION

CHIP WITH POWER-GLITCH DETECTION AND POWER-GLITCH SELF-TESTING

CONTAINERIZED ORCHESTRATION OF SECURE SOCKET LAYER VIRTUAL PRIVATE NETWORK BENCHMARKING

METHOD AND APPARATUS FOR DETECTION OF COUNTERFEIT PARTS, COMPROMISED OR TAMPERED COMPONENTS OR DEVICES, TAMPERED SYSTEMS SUCH AS LOCAL COMMUNICATION NETWORKS, AND FOR SECURE IDENTIFICATION OF COMPONENTS

Secure chip capable of generating secure data by itself

SYSTEMS AND METHODS FOR TESTING INTEGRATED CIRCUITS INDEPENDENT OF CHIP PACKAGE CONFIGURATION

ADHESIVE COMPOSITION AND METHODS OF FORMING THE SAME

Supply Chain Security for Chiplets

SYSTEM FOR AUTOMATED DATA RETRIEVAL FROM AN INTEGRATED CIRCUIT FOR EVENT ANALYSIS

METHOD AND APPARATUS TO DETECT COMPUTING SYSTEM HARDWARE DEFECTS USING A PORTABLE STORAGE DEVICE

METHOD AND SYSTEM FOR CONTROLLING ACTIONS OF TESTBENCH COMPONENTS WITHIN A TEST ENVIRONMENT

CLASSIFYING COMPARATORS BASED ON COMPARATOR OFFSETS

PROTECTION OF THE CONTENT OF A FUSE MEMORY

Method and system for controlling actions of testbench components within a test environment

SCAN CHAIN SECURITY CIRCUIT AND DRIVING METHOD THEREOF

TEST MODE CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS AND SYSTEM, AND METHOD THEREOF

Secure Remote Debugging

MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING STORAGE DEVICE

CONTAINERIZED ORCHESTRATION OF SECURE SOCKET LAYER VIRTUAL PRIVATE NETWORK BENCHMARKING

Invisible scan architecture for secure testing of digital designs

CHIP WITH POWER-GLITCH DETECTION AND POWER-GLITCH SELF-TESTING

AUTHENTICATING ELECTRONIC DEVICES VIA MULTI TONE ANALYSIS

System on chip for performing scan test and method of designing the same

SEMICONDUCTOR INTEGRATED CIRCUIT, A METHOD FOR TESTING THE SEMICONDUCTOR INTEGRATED CIRCUIT, AND A SEMICONDUCTOR SYSTEM

FPGA chip with protected JTAG interface

Method for detecting perturbations in a logic circuit and logic circuit for implementing this method

METHOD FOR CONTROLLING DROP TEST EQUIPMENT

Baseboard management controller (BMC) test system and method

A METHOD AND APPARATUS FOR DETECTION OF COUNTERFEIT PARTS, COMPROMISED OR TAMPERED COMPONENTS OR DEVICES, TAMPERED SYSTEMS SUCH AS LOCAL COMMUNICATION NETWORKS, AND FOR SECURE IDENTIFICATION OF COMPONENTS

SECURED DEBUG

Protection of the content of a fuse memory

Using embedded time-varying code generator to provide secure access to embedded content in an on-chip access architecture

Integrated circuit applicable to performing system protection through dynamic voltage change

Systems and methods for intellectual property-secured, remote debugging

Electronic component testing system and time certification method

Quantitative digital sensor

Trigger activation by repeated maximal clique sampling

Systems and methods for intellectual property-secured, remote debugging

Method for managing a return of a product for analysis and corresponding product

Secured system for testing and maintenance of bulk electrical systems (BES) assets

Detection of pulse width tampering of signals

Classifying comparators based on comparator offsets

Method for detecting at least one glitch in an electrical signal and device for implementing this method

Adhesive composition and methods of forming the same

Secure coprocessor assisted hardware debugging

System and method to secure FPGA card debug ports

Secure debug system for electronic devices

Secure device state apparatus and method and lifecycle management

Method for managing a return of a product for analysis and corresponding product

Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture

Integrated circuit chip stack

Testing resistance of a circuit to a side channel analysis

MICROPROCESSOR INTERFACES

JTAG lockout for embedded processors in programmable devices

Device and method for detecting points of failures

Secure device state apparatus and method and lifecycle management

On-chip monitor circuit and semiconductor chip

Secured method for testing and maintenance of bulk electrical systems (BES) assets

Debug architecture

Method of protecting a circuit against a side-channel analysis

Method of testing the resistance of a circuit to a side channel analysis

Method of testing the resistance of a circuit to a side channel analysis of second order or more

Method of testing the resistance of a circuit to a side channel analysis of second order or more

Method of testing the resistance of a circuit to a side channel analysis

System and apparatus for trusted and secure test ports of integrated circuit devices

Test point-enhanced hardware security

System on chip and secure debugging method

Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture

System and method for establishing a trusted diagnosis/debugging agent over a closed commodity device

Delayed authentication debug policy

Debug architecture

Security system and methods for integrated devices

Data processing system with temperature monitoring for security

Semiconductor apparatus and method of operating the same

Secure low voltage testing

Protecting chip settings using secured scan chains

Integrated circuit with distributed clock tampering detectors

Fault protection for high-fanout signal distribution circuitry

Detection of fault injection attacks using high-fanout networks

Method and apparatus for limiting access to an integrated circuit (IC)

Protection method for data information about electronic device and protection circuit therefor

Remote station and method for re-enabling a disabled debug capability in a system-on-a-chip device

Integrated circuit authentication

Protecting information processing system secrets from debug attacks

Method for producing an electronic device with a disabled sensitive mode, and method for transforming such an electronic device to re-activate its sensitive mode

Protection of proprietary embedded instruments

Secure boot information with validation control data specifying a validation technique

Security parameter zeroization

Access to memory region including confidential information

Transition between states in a processor

Die, chip, method for driving a die or a chip and method for manufacturing a die or a chip

System for detecting a laser attack on an integrated circuit chip

Method and apparatus for limiting access to an integrated circuit (IC)

Debug architecture

System and method for detecting integrated circuit anomalies

Integrated silicon circuit comprising a physicallly non-reproducible function, and method and system for testing such a circuit

Apparatus for protecting against external attack for processor based on arm core and method using the same

Apparatuses, integrated circuits, and methods for testmode security systems

Storing event data and a time value in memory with an event logging module

MEMORY ACCESS UNLOCK

MICROPROCESSOR TESTING CIRCUIT

First and second voltage measurements to adjust a voltage measurer

Device for disturbing the operation of an integrated circuit

Security-protection of a wafer of electronic circuits

Protecting chip settings using secured scan chains

Method for characterizing integrated circuits for identification or security purposes

Hacking detecting device, integrated circuit and method of detecting a hacking attempt

System-on-a-chip (SoC) test interface security

DEVICE FOR SECURING A JTAG TYPE BUS

APPARATUS AND METHOD OF AUTHENTICATING JOINT TEST ACTION GROUP (JTAG)

Apparatus and method for override access to a secured programmable fuse array

Integrated Circuit, Method and Electronic Apparatus

Method and apparatus for providing scan chain security

Method for testing cryptographic circuits, secured cryptographic circuit capable of being tested, and method for wiring such circuit

Methods, apparatuses, and products for a secure circuit

Circuit with testable circuit coupled to privileged information supply circuit

Protection of proprietary embedded instruments

Integrated circuit having secure access to test modes

Testing of an integrated circuit that contains secret information

Testing of an integrated circuit that contains secret information

Secure scan design

Method and apparatus for controlling enablement of JTAG interface

Apparatus and method of authenticating joint test action group (JTAG)

Protecting data on integrated circuit

DEBUG SECURITY LOGIC

Device for defeating reverse engineering of integrated circuits by optical means

Methods, apparatuses, and products for a secure circuit

Device for defeating reverse engineering of integrated circuits by optical means

Device for defeating reverse engineering of integrated circuits by optical means

Providing trusted access to a JTAG scan interface in a microprocessor

Integrated circuit and a method for secure testing

Controlling access to an embedded memory of a microcontroller

Programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof

Implementing logic security feature for disabling integrated circuit test ports ability to scanout data

Protecting an integrated circuit test mode

SEMICONDUCTOR DEVICE AND TEST MODE CONTROL CIRCUIT

System and method for testing a data storage device without revealing memory content

MEDICAL DEVICE AND TEST METHOD FOR MEDICAL DEVICE

Device and method for testing integrated circuit dice in an integrated circuit module

System debug and trace system and method, and applications thereof

Method for defeating reverse engineering of integrated circuits by optical means

INTEGRATED CIRCUIT FOR BEING APPLIED TO ELECTRONIC DEVICE, AND ASSOCIATED TESTING SYSTEM

Hibernating a processing apparatus for processing secure data

Integrated circuit having configurable cells and a secured test mode

Detection of a digital counter malfunction

Method and system for protecting processors from unauthorized debug access

Method for characterizing integrated circuits for identification or security purposes

Electronic circuit comprising a test mode secured by insertion of decoy data in the test chain, associated method

System-on-a-chip (SoC) test interface security

Semiconductor integrated circuit

System and method for testing a data storage device without revealing memory content

Integrated circuit comprising a test mode secured by the use of an identifier, and associated method

External key to provide protection to devices

Electronic circuit comprising a test mode secured by the breaking of a test chain, and associated electronic circuit

Method and apparatus for secure scan testing

Testing circuit and testing method for semiconductor device and semiconductor chip

Detector circuit for detecting an external manipulation of an electrical circuit, circuit arrangement comprising a plurality of detector circuits, memory device and method for operating a detector circuit

Connector ports for anti-tamper

Verification of Performance Attributes of Packaged Integrated Circuits

Protection of a digital quantity contained in an integrated circuit comprising a JTAG interface

Electronic circuit comprising a secret sub-module

System and method for glitch detection in a secure microcontroller

Method and system for selectively masking test responses

Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit

Integrated circuit comprising a test mode secured by detection of the state of a control signal

Device for defeating reverse engineering of integrated circuits by optical means

Method and system for protecting processors from unauthorized debug access

Test access control for secure integrated circuits

Device and method for testing integrated circuit dice in an integrated circuit module

Securing the test mode of an integrated circuit

Integrated circuit disabling

Data processing apparatus, program, and method for testing a secured circuit and maintaining confidentiality of the circuit

Semiconductor apparatus

Method and system for blocking data in scan registers from being shifted out of a device

Lockstep mechanism to ensure security in hardware at power-up

System and method for testing a data storage device without revealing memory content

Device for protection against error injection into an asynchronous logic block of an elementary logic module

Method and system for protecting content in a programmable system

Semiconductor integrated circuit device and test method thereof

Device for protection against error injection into a synchronous flip-flop of an elementary logic module

Provisioning and use of security tokens to enable automated test equipment

Method and apparatus for transferring hidden signals in a boundary scan test interface

Method and apparatus for accessing hidden data in a boundary scan test interface

Integrated circuit comprising a test mode secured by initialization of the test mode

Method of securing the test mode of an integrated circuit via intrusion detection

Protecting an integrated circuit test mode

System and method for securing an integrated circuit as against subsequent reprogramming

Integrated circuit outputs protection during JTAG board tests

Methods and structure for scan testing of secure systems

System-on-chip having secure debug mode

Securing access to integrated circuit scan mode and data

Method and apparatus for securely configuring parameters of a system-on-a-chip (SOC)