AI EMBEDDING VECTOR DATA BASE CALIBRATION ARCHITECTURE

GENERATING A TEST PROGRAM

ELECTRONIC DEVICE FOR IMPROVING A PERFORMANCE OF A SIGNAL CHAIN

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER

TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

Scan testing using scan frames with embedded commands

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Test compression in a JTAG daisy-chain environment

Test circuit in chip and circuit test method

Chip test circuit and circuit test method

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Reduced signaling interface method and apparatus

Single “A” latch with an array of “B” latches

Test apparatus and test method to a memory device

Method and circuit for scan dump of latch array

Method and circuit for row scannable latch array

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Scan testing using scan frames with embedded commands

Automated overclocking using a prediction model

Test compression in a JTAG daisy-chain environment

Integrated circuit with reduced signaling interface

Scheme applied in JTAG TAP apparatus, JTAG host, and target system capable of achieving data verification as well as saving on-chip circuit costs

Test method and test system

Logic built-in self test dynamic weight selection method

Systems and methods for predicting the trajectory of an object with the aid of a location-specific latent map

Electronic control unit testing optimization

Programmable scan compression

Reduced signaling interface circuit

Electrical circuit for testing primary internal signals of an ASIC

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Test compression in a JTAG daisy-chain environment

Batch testing system and method thereof

IC test architecture having differential data input and output buffers

Optimization and scheduling of the handling of devices in the automation process

Apparatus, method, and storage medium

Programmable scan compression

Reconfiguring monitoring circuitry

Extracting debug information from FPGAs in multi-tenant environments

Signal probability-based test cube reordering and merging

Entering home state after soft reset signal after address match

TCK to shift register and decompressor on shift-DR and pause-DR

Single pin test interface for pin limited systems

Pin connection testing system for connector, and method thereof

First tap, test compression architecture; second tap, test compression architecture

Panel testing device

HIGHLY EFFICIENT DOUBLE-SAMPLING ARCHITECTURES

Method and device for calibrating an automated test equipment

Input shift register having parallel serial scan outputs, command output

Non-destructive recirculation test support for integrated circuits

Test compression in a JTAG daisy-chain environment

Reconfiguring debug circuitry

Tap, decoder providing SC and SE to scan path circuits

Address/instruction registers, target domain interfaces, control information controlling all domains

Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO

Testing a board assembly using test cards

HIGHLY EFFICIENT DOUBLE-SAMPLING ARCHITECTURES

I/O control circuit for reduced pin count (RPC) device testing

Extracting debug information from FPGAs in multi-tenant environments

Decompressed/compressed data parallel scan paths with tap decoded shift/scan clocks

Differential I/O for parallel scan paths, scan frames, embedded commands

Bypassing an encoded latch on a chip during a test-pattern scan

Bypassing an encoded latch on a chip during a test-pattern scan

Double data rate circuitry coupled to test access mechanisms, controller

Control I/O coupling scan test port to test access port

Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs

HIGHLY EFFICIENT DOUBLE-SAMPLING ARCHITECTURES

Test method and test apparatus for testing a plurality of blocks in a circuit

Secure remote debugging of SoCs

Debugging method executed via scan chain for scan test and related circuitry system

Dynamic process for adaptive tests

Test point-enhanced hardware security

IC cores, scan paths, compare circuitry, select and enable inputs

Addressable tap domain selection circuit with instruction and linking circuits

TDI, SC, and SE gating circuitry with count complete input

Tap SPC with tap state machine reset and clock control

Reconfiguring debug circuitry

CHIP AND METHOD FOR TESTING A PROCESSING COMPONENT OF A CHIP

Method and apparatus for test time reduction using fractional data packing

Scan testing scan frames with embedded commands and differential signaling

Method and apparatus for obtaining a maximally compressed verification test set

Scheme for Masking Output of Scan Chains in Test Circuit

METHODS AND SYSTEMS FOR TRANSFORMING FAULT TREE DIAGRAMS OF ENGINEERING SYSTEMS

Programmable circuits for correcting scan-test circuitry defects in integrated circuit designs

IC and process shifting compressed data and loading scan paths

Tap controller state machine scanning capturing plurality of scan paths

Bypass register separately controlled as internal scan circuit by TAP

Electronic device with chip-on-film package

Tester for integrated circuits on a silicon wafer and integrated circuit

Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO

METHODS AND DEVICES FOR DETERMINING LOGICAL TO PHYSICAL MAPPING ON AN INTEGRATED CIRCUIT

Modifying a scan chain for improved fault diagnosis of integrated circuits

Inserting bypass structures at tap points to reduce latch dependency during scan testing

Inserting bypass structures at tap points to reduce latch dependency during scan testing

Structural testing of integrated circuits

Implementing fixed-point polynomials in hardware logic

Serial/parallel control, separate tap, master reset synchronizer for tap domains

TEST CIRCUIT DESIGN APPARATUS, TEST CIRCUIT DESIGN PROGRAM, AND TEST CIRCUIT

Test clock/test mode slect (TCK/TMS), select, data register (DR) connection circuitry between test access port (TAP) and bypass register

TAP addressable circuit with bi-directional TMS and second signal lead

Gated state machine circuitry having three clock 2 enable states

Device for generating test pattern

Design-Based weighting for logic built-in self-test

IC tap/scan selecting between TDI/SI and a test pattern source

Linking circuitry selectively coupling TDI/TDO with first and second domains

Operating state machine from reset to poll in to reset

Systems and methods for test time outlier detection and correction in integrated circuit testing

Asynchronous programmable JTAG-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic

Electronic device with chip-on-film package

Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip

Circuitry selectively coupling scan circuitry to test data out lead

On-chip spectral analysis using enhanced recursive discrete Fourier transforms

Scan test controller with state machine and gates

Methods and devices for determining logical to physical mapping on an integrated circuit

Methods and structure for utilizing external interfaces used during normal operation of a circuit to output test signals

Transitioning POLL IN to set MRST and CE high states

Testing an integrated circuit device with multiple testing protocols

Maximizing Re-Use of External Pins of an Integrated Circuit for Testing

Systems and methods for test time outlier detection and correction in integrated circuit testing

Testing integrated circuits using few test probes

Circuit test interface and test method thereof

IC with wrapper, TAM, TAM controller, and DDR circuitry

Test access and scan test ports with lockout signal terminal

Gating of clock-DR and pause-DR from TAP to TCA

Parallel scan paths with stimulus and header data circuitry

Master reset and synchronizer circuit with data and clock inputs

DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE

Address and instruction controller with TCK, TMS, address match inputs

Compare circuitry with scan cell separate from serial scan circuitry

Integrated circuit having a scan chain and testing method for a chip

Programmable test compression architecture with serial input register and multiplexer

IR gating SC signals during TAP Clock-DR and Pause-DR states

Tap and scan test port with IR lock out output

Semiconductor integrated circuit, circuit testing system, circuit testing unit, and circuit test method

Integrated circuit arrangement for test inputs

Core circuit test architecture

Scan paths, stimulus, and header circuitry with command/frame marker outputs

Testing integrated circuits

Clock controller for JTAG interface

Semiconductor device for performing test operation and method thereof

Systems and methods for test time outlier detection and correction in integrated circuit testing

Inverter and TMS clocked flip-flop pairs between TCK and reset

DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE

Tap and control with data I/O, TMS, TDI, and TDO

Method and SOC for implementing time division multiplex of pin

Multiplexer selecting STP clock signal with tap control outputs

Reduced signaling interface method and apparatus

Gating circuitry coupling selected scan paths between I/O scan bus

Optimized JTAG interface

Tap control of TCA scan clock and scan enable

Serial compressed data I/O in a parallel test compression architecture

DDR gate and delay clock circuitry for parallel interface registers

Dual mode test access port method and apparatus

Core circuit test architecture

SEMICONDUCTOR INTEGRATED CIRCUIT

Test method and program product used therefor

Optimized JTAG interface

Reduced signaling interface method and apparatus

Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip

Parallel scan paths with header data circuitry and header return circuitry

MULTI-CHIP PACKAGE FOR REDUCING TEST TIME

Testing integrated circuits using few test probes

Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test

Systems and methods for test time outlier detection and correction in integrated circuit testing

DDR register circuitry input to IC test controller circuitry

Voltage adjusting circuits and voltage adjusting methods

Semiconductor integrated circuit

Scan output connection in tap and scan test port

MULTIPLEXING OF SCAN INPUTS AND SCAN OUTPUTS ON TEST PINS FOR TESTING OF AN INTEGRATED CIRCUIT

Local and global address compare with tap interface TDI/TDO lead

Test circuit capable of masking data at read operation and method for controlling the same

Microelectronic device and pin arrangement method thereof

Providing A Duplicate Test Signal Of An Output Signal Under Test In An Integrated Circuit

Optimized JTAG interface

Device and method for configuring input/output pads

Test Sequence Optimization Method and Design Tool

Self-reparable semiconductor and method thereof

Apparatus and method for flexible visibility in integrated circuits with minimal package impact

Semiconductor integrated circuit and system LSI having a test expected value programming circuit

CORE CIRCUIT TEST ARCHITECTURE

Synthetic instrument utilizing peer-to-peer communication for error correction

Electronic device having an interface supported testing mode

DDR input interface to IC test controller circuitry

TAP, ST, lockout, and IR SO enable output data control

Scan testing using scan frames with embedded commands

Integrated device for simplified parallel testing, test board for testing a plurality of integrated devices, and test system and tester unit

Ultra low pin count interface for die testing

Hardware enablement using an interface

Connector ports for anti-tamper

Reduced pin count scan chain implementation

Fuse circuit with leakage path elimination

Methods for slow test time detection of an integrated circuit during parallel testing

Semiconductor device, test system and method of testing on die termination circuit

Design-for-test circuit for low pin count devices

Design data structure for semiconductor integrated circuit and apparatus and method for designing the same

Apparatus and method for a single wire interface between a intergated circuit and JTAG test and emulation apparatus

Method and apparatus for parameter adjustment, testing, and configuration

Semiconductor integrated circuit device

Optimize parallel testing

Electronic device having an interface supported testing mode

Controller receiving combined TMS/TDI and suppyling separate TMS and TDI

Semiconductor device tested using minimum pins and methods of testing the same

Method for testing a circuit unit and test apparatus

Semiconductor test circuit

Structured integrated circuit device

Systems and methods for facilitating testing of integrated circuits

Addressable tap domain selection circuit with TDI/TDO external terminal

Latch circuit including a data retention latch

Shared bond pad for testing a memory within a packaged semiconductor device

Multi-chip package for reducing test time

Semiconductor device and evaluation circuit for the same

Method and system of generic implementation of sharing test pins with I/O cells

Low cost test for IC's or electrical modules using standard reconfigurable logic devices

System and method of digital system performance enhancement

IC with TAP, STP and lock out controlled output buffer

Compacting circuit responses

Structured integrated circuit device

Structured integrated circuit device

Trace information queueing system

Reduced pin count test method and apparatus

Single-ended transmission for direct access test mode within a differential input and output circuit

Reducing Number of Pins Required to Test Integrated Circuits

Interface circuit for a single logic input pin of an electronic system

Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit

IC with parallel scan paths and compare circuitry

Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components

Self-reparable semiconductor and method thereof

System and method for evaluating the speed of a circuit

Semiconductor integrated circuit having a number of data output pins capable of selectively providing output signals and test method thereof

System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test

Scalable scan architecture for multi-circuit block arrays

Removal of over-masking in an on product multiple input signature register (OPMISR) test

Minimization of over-masking in an on product multiple input signature register (OPMISR)

Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through spreading in stumpmux daisy-chain structure

Sharing a JTAG interface among multiple partitions

Flip-flop with delineated layout for reduced footprint

Configuration of semiconductor device supply voltage