DEBUG INFRASTRUCTURE FOR MEMORY SYSTEMS

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

PATTERN GENERATION SYSTEM WITH PIN FUNCTION MAPPING

Yield improvements for three-dimensionally stacked neural network accelerators

BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING THE SAME

Integrated circuit having test circuitry for memory sub-systems

Selectable JTAG or trace access with data store and output

Method for checking DFT circuit, test platform, storage medium and test system

Processing system, related integrated circuit, device and method

Addressable test chip test system

Test circuit in chip and circuit test method

Chip test circuit and circuit test method

Reduced signaling interface method and apparatus

Benchmark circuit on a semiconductor wafer and method for operating the same

SYSTEMS AND DEVICES FOR INTELLIGENT INTEGRATED TESTING

REAL-EQUIVALENT-TIME FLASH ARRAY DIGITIZER OSCILLOSCOPE ARCHITECTURE

Pattern generation system with pin function mapping

Selectable JTAG or trace access with data store and output

Addressable test chip

Method for allocating addresses and corresponding units

Distributed control system, automatic analysis device, and automatic analysis system

Integrated circuit with reduced signaling interface

Random number generation testing systems and methods

SYSTEM FOR TEST AND MEASUREMENT INSTRUMENTATION DATA COLLECTION AND EXCHANGE

System and method for distributed execution of a sequence processing chain

Reduced signaling interface circuit

Interfaces for wireless debugging

Selectable JTAG or trace access with data store and output

Addressable test system with address register

Testing fuse configurations in semiconductor devices

Entering home state after soft reset signal after address match

Functional, tap, trace circuitry with multiplexed tap, trace data output

Addressable test chip with sensing circuit

Addressable test chip with multiple-stage transmission gates

Memory circuit march testing

Single pin test interface for pin limited systems

Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit

Interfaces for wireless debugging

Trace domain controller with test data I/O/control, internal control I/O

Addressable test chip test system

Address/instruction registers, target domain interfaces, control information controlling all domains

Tap domain selection circuit with AUX buffers and multiplexer

Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit

Semiconductor device method relating to latch circuit testing

Portion isolation architecture for chip isolation test

Partition-able storage of test results using inactive storage elements

One tap domain coupling two trace circuits, address command port

Design-for-Test Techniques for a Digital Electronic Circuit

Testing fuse configurations in semiconductor devices

Interfaces for wireless debugging

Addressable test access port domain selection circuitry TCK logic gate

Addressable tap domain selection circuit with instruction and linking circuits

Address-command port connected to trace circuits and tap domains

DEBUGGER AND DEBUGGING SYSTEM

Test system that performs simultaneous tests of multiple test units

TAP addressable circuit with bi-directional TMS and second signal lead

Automated test system with event detection capability

Linking circuitry selectively coupling TDI/TDO with first and second domains

Testing fuse configurations in semiconductor devices

Connection system and simulator using such a connection system

Address and command port connecting trace circuitry and TAP domain

Address and instruction controller with TCK, TMS, address match inputs

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

Tap interface select circuit with AUX1/02-TMS and TMS/RCK-RCK leads

Testing fuse configurations in semiconductor devices

TAP interface select circuit with TMS/RCK or RCK lead

System and method for wirelessly testing integrated circuits

Inverter and TMS clocked flip-flop pairs between TCK and reset

Reduced signaling interface method and apparatus

Reduced signaling interface method and apparatus

Communication between controller and addressed target devices over data signal

DEVICE TEST AND DEBUG USING POWER AND GROUND TERMINALS

Test mode for multi-chip integrated circuit packages

Reduced signaling interface method and apparatus

Selectable JTAG or trace access with data store and output

Reduced signaling interface method and apparatus

TAP domain selection circuit with selected TDI/TDO or TDO lead

Selectable JTAG or trace access with data store and output

Automatically extensible addressing for shared array built-in self-test (ABIST) circuitry

Semiconductor device including address signal generating protion and digital-to-analog converter

Applying test response start and command signals to power lead

Local and global address compare with tap interface TDI/TDO lead

Isolation of unverified devices in a SAS expander

Testing fuse configurations in semiconductor devices

M1 testable addressable array for device parameter characterization

STACKED PACKAGE SCREENING

Clock signal distributing circuit, information processing device and clock signal distributing method

Circuit and Method for Physical Defect Detection of an Integrated Circuit

Memory wrap test mode using functional read/write buffers

TAP domain selection circuit with AUXI/O1 or TDI lead

Selecting test circuitry from header signals on power lead

Test mode for multi-chip integrated circuit packages

Systems and methods for chip testing

Apparatus and method for discrete test access control of multiple cores

Semiconductor integrated circuit device and inspection method therefor

Versatile semiconductor test structure array

Multi-module simultaneous program, erase test, and performance method for flash memory

Test device and method for circuit device and manufacturing method for the same

Signal integrity self-test architecture

Selectable JTAG or trace access with data store and output

Method and apparatus to verify non-deterministic results in an efficient random manner

Shared memory bus architecture for system with processor and memory units

Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer

System for testing smart cards and method for same

Defect analysis using a yield vehicle

Memory self-test via a ring bus in a data processing apparatus

Provision of debug via a separate ring bus in a data processing apparatus

Addressable tap domain selection circuit with selectable ⅗ pin interface

Addressable tap domain selection circuit with TDI/TDO external terminal

Method for generating identification code of semiconductor device, method for identifying semiconductor device and semiconductor device

Test apparatus and method for testing circuit units to be tested

Adaptive communication methods and apparatus

Memory profiler for emulation

Electronic system and signal switching circuit