RECEPTION SIGNAL QUALITY MONITOR

FUNCTIONAL EVENT MANAGEMENT SYSTEM AND METHOD

METHOD PERFORMED BY A DIFFERENTIAL RELAYING PROTECTION APPARATUS

CIRCUIT AND METHOD FOR INTERCONNECT TEST

JTAG-BASED APPARATUS AND METHOD FOR INPUT CLOCK FREQUENCY MEASUREMENT

SENSOR CIRCUIT AND METHOD

SYSTEM AND METHOD FOR AREA-EFFICIENT MONITORING OF CLOCK SIGNALS

APPARATUS AND METHOD FOR IMPLEMENTING A SCALABLE DIGITAL INFRASTRUCTURE FOR MEASURING RING OSCILLATORS

DIE-TO-DIE AND CHIP-TO-CHIP INTERCONNECT CLOCK SKEW COMPENSATION

SCAN FLIP-FLOP

SMART GRID INTERFACE RELAY AND BREAKER

Signal integrity monitoring system

SCAN CLOCK GATING CONTROLLER AND METHOD FOR PERFORMING STUCK-AT FAULT TEST AMONG MULTIPLE BLOCK CIRCUITS

TEST SYSTEM

DETECTION METHOD AND APPARATUS FOR LINK, ELECTRONIC DEVICE AND COMPUTER-READABLE MEDIUM

Time-to-digital converter circuit with self-testing function

TRANSMITTER FOR ULTRA-HIGH SPEED AND STORAGE DEVICE INCLUDING THE SAME

Smart grid interface relay and breaker

Selecting an Output as a System Output Responsive to an Indication of an Error

COMPUTER-READABLE RECORDING MEDIUM STORING TEST PATTERN GENERATION PROGRAM, TEST PATTERN GENERATION APPARATUS, AND TEST PATTERN GENERATION METHOD

PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS OF A PROCESSOR

TRAINING METHOD AND TEST APPARATUS USING THE SAME

Fault tolerant synchronizer

Testing circuitry for testing multicycle path circuit

Testing system and testing method

IN-CIRCUIT EMULATOR DEVICE

Methods and apparatus for testing inaccessible interface circuits in a semiconductor device

Smart grid interface relay and breaker

On-chip oscilloscope

Time offset method and device for test signal

APPARATUS AND METHOD FOR IMPLEMENTING A SCALABLE DIGITAL INFRASTRUCTURE FOR MEASURING RING OSCILLATORS

Semiconductor device and method for generating test pulse signals

Memory controller with integrated test circuitry

TEST AND MEASUREMENT SYSTEM

Techniques For Reduction Of Degradation In Channels Caused By Bias Temperature Instability

Circuit for transferring data from one clock domain to another

Transition fault testing of functionally asynchronous paths in an integrated circuit

Device under test synchronization with automated test equipment check cycle

Fault tolerant synchronizer

Automated testing machine with data processing function and information processing method thereof

Electronic component testing system and time certification method

Clock frequency monitoring device and clock frequency monitoring method

Method and apparatus for determining jitter, storage medium and electronic device

DIGITAL CIRCUIT MONITORING DEVICE

On-chip oscilloscope

Digital circuit robustness verification method and system

Memory controller with integrated test circuitry

Auto-calibration circuit for pulse generating circuit used in resonating circuits

Device and method for data preservation and power loss recovery in an electric meter

Data transmission apparatus and data transmission method

Test apparatus and test method

Two pin scan interface for low pin count devices

Fault tolerant synchronizer

Method for calibrating channel delay skew of automatic test equipment

Debugging a semiconductor device

Memory loopback systems and methods

Device and method for data preservation and power loss recovery in an electric meter

Method of measuring clock jitter, clock jitter measurement circuit, and semiconductor devices including the same

Semiconductor device

Memory controller with integrated test circuitry

Transistion fault testing of funtionally asynchronous paths in an integrated circuit

Eye pattern generator

On-chip oscilloscope

Transition scan coverage for cross clock domain logic

Memory loopback systems and methods

Multichip reference logging synchronization

Method of measuring clock jitter, clock jitter measurement circuit, and semiconductor device including the same

Device throughput optimization for bus protocols

Time-aligning communication channels

Receiver clock test circuitry and related methods and apparatuses

Method, and a synchronous digital circuit, for preventing propagation of set-up timing data errors

Lightweight, low overhead debug bus

Scannable data synchronizer

Granular dynamic test systems and methods

On-chip oscilloscope

Static timing analysis in circuit design

Self-test circuit in integrated circuit, and data processing circuit

Receiver clock test circuitry and related methods and apparatuses

Test structure to measure delay variability mismatch of digital logic paths

Methods and apparatus for testing inaccessible interface circuits in a semiconductor device

Static timing analysis in circuit design

Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuit

Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test

FAILURE DIAGNOSIS SYSTEM, FAILURE DIAGNOSIS METHOD, AND FAILURE DIAGNOSIS PROGRAM

Test path compensating circuit and test path compensating system

Cycle deterministic functional testing of a chip with asynchronous clock domains

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Synchronous sampling of internal state for investigation of digital systems

First and second data communication circuitry operating in different states

Timing skew characterization apparatus and method

Memory channel having deskew separate from redrive

Device under test data processing techniques

Managing IR drop

On-die all-digital delay measurement circuit

Adaptive digital delay line for characterization of clock uncertainties

System and method for verifying the operating frequency of digital control circuitry

Packet switch based logic replication

Analysis method for signal time margin

Clock and mode signals for header and data communications

Methods and apparatus for testing inaccessible interface circuits in a semiconductor device

Receiver clock test circuitry and related methods and apparatuses

System and method for verifying the operating frequency of digital control circuitry

Test apparatus and test method

Semiconductor integrated circuit

Test path selection and test program generation for performance testing integrated circuit chips

Automatic generation of valid at-speed structural test (ASST) test groups

Integrated circuit device, electronic device and method for detecting timing violations within a clock signal

System and method for testing integrated circuits by determining the solid timing window

Selection circuit with only idel, capture, shift, and update states

BIST circuit for phase measurement

Clock domain check method, clock domain check program, and recording medium

Test apparatus and test method

Flip-flop circuit, scan test circuit, and method of controlling scan test circuit

Timing skew characterization apparatus and method

Semiconductor Integrated Circuit

Method of testing asynchronous modules in semiconductor device

Structure and method of data synchronization for Multi measuring apparatus

Memory channel having deskew separate from redrive

Clock edge grouping for at-speed test

Phase interpolator, semiconductor device and testing method thereof

Selection circuit enabling clock/mode or mode/clock signals

TEST APPARATUS, CALIBRATION METHOD AND RECORDING MEDIUM

Self-adjusting critical path timing of multi-core VLSI chip

TEST APPARATUS AND TEST METHOD

Test apparatus and test method

Test apparatus, transmission apparatus, receiving apparatus, test method, transmission method and receiving method

Data processing unit and a method of processing data

Semiconductor device and diagnostic method thereof

Packet switch based logic replication

Test apparatus and synchronization method

Inter-phase skew detection circuit for multi-phase clock, inter-phase skew adjustment circuit, and semiconductor integrated circuit

Semiconductor device

Method and system for correcting error in a PLL generated clock signal using a system clock of lower frequency and/or accuracy

Clock and mode signals controlling data communication in three states

Test apparatus and test method

Low overhead circuit and method for predicting timing errors

Test method using memory programmed with tests and protocol to communicate between device under test and tester

Test apparatus

Failure prediction circuit and method, and semiconductor integrated circuit

Method and circuit of calibrating data strobe signal in memory controller

Test apparatus

Method for synchronizing a plurality of measuring channel assemblies and/or measuring devices, and appropriate measuring device

Plural circuit selection using role reversing control inputs

Method and apparatus for detecting and correcting errors in a parallel to serial circuit

METHOD, APPARATUS, AND PROGRAM FOR CORRECTING HOLD ERROR

MEASUREMENT APPARATUS FOR IMPROVING PERFORMANCE OF STANDARD CELL LIBRARY

Method for determining time differences between signals measured by at least two coupled measuring devices and measurement system and corresponding switching device

Semiconductor device having built-in self-test circuit and method of testing the same

Hardware and method to test phase linearity of phase synthesizer

Jitter evaluation

Method and apparatus for late timing transition detection

Clock domain check method, clock domain check program, and recording medium

Signal measuring device and signal measuring method

Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core

Tracker circuit and method for automated test equipment systems

Method and apparatus for calibrating internal pulses in an integrated circuit

SEMICONDUCTOR DEVICE

Systemic Frequency Adjusting Method for Storage Device

Data transfer device and method thereof

Circuit arrangement, apparatus and process for the serial sending of data via a connection contact

In-circuit programming of output voltage and output current characteristics of a PSR power supply

Semiconductor integrated circuit

Plural circuit selection using role reversing control inputs

Signal phase verification for systems incorporating two synchronous clock domains

Semiconductor integrated circuit

Timing signal generator providing synchronized timing signals at non-integer clock multiples adjustable by more than one period

Adjustable test pattern results latency

Apparatus for distributing a signal

Semiconductor device, memory system and control method of the semiconductor device

Circuit and method for integrated circuit configuration

APPARATUS AND METHOD FOR MEASURING SKEW IN SERIAL DATA COMMUNICATION

Power supply voltage detection circuit and semiconductor integrated circuit device

Bit pattern synchronization in acquired waveforms

Method and apparatus for calibrating internal pulses in an integrated circuit

Frequency monitor

Clock distribution circuit and test method

Plural circuit selection using role reversing control inputs

Aligning timebases to share synchronized periodic signals

Method for checking the integrity of a clock tree

Embedded time domain analyzer for high speed circuits

Method and apparatus for measuring the duty cycle of a digital signal

Semiconductor device, and test circuit and test method for testing semiconductor device

Inspection support apparatus and inspection support method

Plesiochronous transmit pin with synchronous mode for testing on ATE

Circuit timing monitor having a selectable-path ring oscillator

Multiple probe acquisition system

Method and system for measuring maximum operating frequency and corresponding duty cycle for an I/O cell

Test apparatus, shift amount measuring apparatus, shift amount measuring method and diagnostic method

Circuits with state circuitry having cross connected control inputs

Synchronizing clock and aligning signals for testing electronic devices

Process for designing a circuit for synchronizing data asychronously exchanged between two synchronous blocks, and synchronization circuit fabricated by same

Method and apparatus for measuring the duty cycle of a digital signal

Test apparatus for regulating a test signal supplied to a device under test and method thereof

Control signal synchronization of a scannable storage circuit

Method and apparatus for on-chip duty cycle measurement

Method for evaluating semiconductor device

Message system for logical synchronization of multiple tester chips

Method and circuit for LSSD testing

Skew adjusting method, skew adjusting apparatus, and test apparatus

Coordinating data synchronous triggers on multiple devices

Error-detection flip-flop

Providing precise timing control between multiple standardized test instrumentation chassis

Plural circuit selection using role reversing control inputs

Method and apparatus for late timing transition detection

Skew correction system eliminating phase ambiguity by using reference multiplication

INTEGRATION CIRCUIT AND TEST METHOD OF THE SAME

Concurrent control of semiconductor parametric testing

Providing precise timing control within a standardized test instrumentation chassis

Circuit card synchronization within a standardized test instrumentation chassis

Built-in waveform edge deskew using digital-locked loops and coincidence detectors in an automated test equipment system

Semiconductor testing apparatus

Methods and apparatus for managing clock skew between clock domain boundaries

Method and apparatus for source synchronous testing

Integrated circuit chip having a first delay circuit trimmed via a second delay circuit

Method for selecting optimum sampling parameters for a plurality of data receivers having at least one sampling parameter in common

Digital system, clock signal adjusting method for digital system, recording medium recording processing program executed in the adjusting method

Signal measurement systems and methods

Modular numerical control having low-jitter synchronization

Synchronization of multiple test instruments

Synchronization of multiple test instruments

Method for evaluating semiconductor device

Selecting between two TAP circuits with MODE/TCK and TCK/MODE signals

Method of adjusting strobe timing and function testing device for semiconductor device

Process parameter based I/O timing programmability using electrical fuse elements

Methods and apparatus for providing test access to asynchronous circuits and systems

Intelligent riser testing device and methods

Debug and trace circuit in lockstep architectures, associated method, processing system, and apparatus

Testing memory elements using an internal testing interface

Synchronized clocks to detect inter-clock domain transition defects

Sharing a JTAG interface among multiple partitions

Circuits for and methods of implementing a design for testing and debugging with dual-edge clocking

Synchronous circuit, method of designing a synchronous circuit, and method of validating a synchronous circuit

Method for marking data in time/frequency measurement