189026 ⎘
Details not covered by groups - and; Generating or distributing clock signals or signals derived directly therefrom; Distribution of clock signals, e.g. skew in which the distribution is at least partially optical
STORAGE SYSTEM
#2POWER AND DATA COUPLING SYSTEM
#3HOUSING WITH MULTI-FUNCTIONAL MODULES
#4ACCESSORY MANAGEMENT APPARATUS
#5CLOCK SIGNAL DISTRIBUTION METHOD
#6Infrastructure article system for synchronizing blinks of infrastructure articles connected in mesh network
#7CHARGING APPARATUS
#8Accessory storage case
#9Optically enabled RF phased-arrays for data transmission
#10Method and system for extractable randomness scaling in quantum random number generators
#11Fiber-optically powered antenna
#12Optical communication drive circuit and method, optical communication transmitter and system, and vehicle
#13MEMORY CONTROLLER
#14Charging and storage system
#15OPTICAL SIGNAL SKEW COMPENSATION
#16Circuit device, electro-optical device, and electronic apparatus
#17Multipurpose accessory and storage system
#18System for transceiving data based on clock transition time
#19Memory controller
#20Storage system for handheld electronic device
#21Clock signal generator
#22Information processing apparatus, method of controlling information processing apparatus, non-transitory storage medium encoded with computer readable program for information processing apparatus, and information processing system
#23Memory controller
#24Memory controller
#25Optical link clock receiver
#26Memory controller
#27Quantum clocks for a master/slave clock architecture
#28Analog optical fiber-based signal distribution system and method
#29Circuit arrangement and method for transmitting signals
#30Memory module
#31Optoelectronic circuit and a method for the transmission of an optical clock signal
#32Memory controller that enforces strobe-to-strobe timing offset
#33Memory component that samples command/address signals in response to both edges of a clock signal
#34Automatic internal trimming calibration method to compensate process variation
#35Memory controller with selective data transmission delay
#36Memory controller
#37Optical clock signal distribution using through-silicon vias
#38Intentionally skewed optical clock signal distribution
#39Automatic internal trimming calibration method to compensate process variation
#40Optical clock signal distribution using through-silicon vias
#41Optical triggered self-timed clock generation
#42Method and apparatus for signaling between devices of a memory system
#43Memory module with termination component
#44Method and an apparatus for providing timing signals to a number of circuits, and integrated circuit and a node
#45Semiconductor integrated circuit
#46Memory controller device having timing offset capability
#47Surface emitting laser with an integrated absorber
#48Skew correction system eliminating phase ambiguity by using reference multiplication
#49Eliminating clock skew by using bidirectional signaling
#50Average time extraction by multiplication
#51DC technique for eliminating phase ambiguity in clocking signals
#52AC technique for eliminating phase ambiguity in clocking signals
#53Average time extraction circuit for eliminating clock skew
#54Average time extraction circuit for eliminating clock skew
#55Digital Logic Unit
#56LSI apparatus operated by optical clock
#57Interface circuit that interconnects a media access controller and an optical line termination transceiver module
#58Method, system and memory controller utilizing adjustable read data delay settings
#59Method, system and memory controller utilizing adjustable write data delay settings
#60Apparatus for extracting optical clock using filters and amplifier and method for the same
#61Memory module with termination component
#62Dual-mode pulse generator
#63Surface emitting laser with an integrated absorber
#64Memory module with termination component
#65Memory device with clock multiplier circuit
#66Systems and methods for measurement-device-independent quantum key distribution
#67Apparatus and method to compensate for data skew for multiple memory devices and adjust delay for individual data lines based on an optimized critical window