189967 ⎘
Error detection; Error correction; Monitoring; Responding to the occurrence of a fault, e.g. fault tolerance; Error detection or correction by redundancy in data representation, e.g. by using checking codes; Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error Error in check bits
MEMORY DEVICE AND IN-MEMORY COMPUTING METHOD FOR BINARIZED NEURAL NETWORK
#2APPARATUSES AND METHODS FOR CONFIGURABLE ECC MODES
#3DETERMINING DATA MIGRATION PRIORITIES IN A MEMORY SUB-SYSTEM
#4ERRONEOUS BIT DISCOVERY IN MEMORY SYSTEM
#5MEMORY ERROR DETECTION AND CORRECTION
#6SEMICONDUCTOR DEVICE WITH MODIFIED ACCESS AND ASSOCIATED METHODS AND SYSTEMS
#7SEMICONDUCTOR MEMORY APPARATUS CONFIGURED TO PERFORM AN ERROR CHECK
#8DATA RECOVERY SYSTEM FOR MEMORY DEVICES
#9MINIMIZING REDUNDANCY FOR STUCK BIT CODING
#10COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN
#11MEMORY DEVICE, OPERATION METHOD OF THE MEMORY DEVICE, AND PROGRAM
#12MEMORY INCLUDING ECC ENGINE AND OPERATION METHOD OF MEMORY
#13DATA PROTECTION METHOD, STORAGE MEDIUM, AND ELECTRONIC DEVICE
#14APPARATUS AND METHOD FOR EFFICIENT ENCODING FOR TRUSTED EXECUTION ENVIRONMENTS WITH FULL ERROR CORRECTION
#15APPARATUS AND METHODS FOR MEMORY FAULT DETECTION WITHIN DIE ARCHITECTURES
#16Data storage device and method for identifying a failing area of memory based on a cluster of bit errors
#17SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
#18VOLTAGE SCALING BASED ON ERROR RATE
#19VOLTAGE SCALING BASED ON ERROR RATE
#20HOST-LEVEL ERROR DETECTION AND FAULT CORRECTION
#21SPARE SUBSTITUTION IN MEMORY SYSTEM
#22COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN
#23Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization
#24Data recovery method for flash memory
#25OPERATION METHOD OF MEMORY CONTROLLER CONFIGURED TO CONTROL MEMORY DEVICE
#26DATA PROCESSING METHOD AND APPARATUS
#27APPARATUSES AND METHODS FOR CONFIGURABLE ECC MODES
#28ERRONEOUS BIT DISCOVERY IN MEMORY SYSTEM
#29HIGH PERFORMANCE PROCESSOR FOR LOW-WAY AND HIGH-LATENCY MEMORY INSTANCES
#30Memory Testing Techniques
#31Command address fault detection using a parity pin
#32METHOD FOR CONTROLLING SECURE BOOT OF VEHICLE CONTROLLER AND SYSTEM THEREOF
#33SEMICONDUCTOR DEVICE WITH MODIFIED ACCESS AND ASSOCIATED METHODS AND SYSTEMS
#34Error correction code circuit and error correction method
#35Memory error detection and correction
#36Spare substitution in memory system
#37Host-level error detection and fault correction
#38Processor with In-Band Fault-Injection Detection in the Presence of Exceptions
#39DDR DIMM, memory system and operation method thereof
#40Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization
#41ADAPTIVE FLOATING POINT INFERENCE PERFORMANCE FOR SYSTEMS WITH UNRELIABLE MEMORY
#42Spare substitution in memory system
#43Introduction and detection of parity error in a UART
#44System, method, and computer program product for generating a data storage server distribution pattern
#45Error control for content-addressable memory
#46Data recovery system for memory devices
#47System and methods for hardware-software cooperative pipeline error detection
#48Detection and correction of data bit errors using error correction codes
#49Erroneous bit discovery in memory system
#50Data recovery system for memory devices
#51MEMORY-BASED DISTRIBUTED PROCESSOR ARCHITECTURE
#52Configurable media structure
#53Memory system and operating method thereof
#54Memory error detection and correction
#55Error signaling windows for phase-differential protocols
#56Data protection system and method thereof for 3D semiconductor device
#57Error correction management for a memory device
#58Memory-based distributed processor architecture
#59Semiconductor device with modified access and associated methods and systems
#60Bit block stream bit error detection method and device
#61Memory sub-system grading and allocation
#62Spare substitution in memory system
#63ZONED NAMESPACE MANAGEMENT OF NON-VOLATILE STORAGE DEVICES
#64Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system
#65MEMORY CONTROL METHOD AND SYSTEM
#66Processing-in-memory (PIM) devices
#67Processing-in-memory (PIM) devices
#68Memory-based distributed processor architecture
#69Memory sub-system grading and allocation
#70Semiconductor device with modified access and associated methods and systems
#71Error control for content-addressable memory
#72Configurable media structure
#73System, method, and computer program product for generating a data storage server distribution pattern
#74Detection and correction of data bit errors using error correction codes
#75Techniques for generating symbol-preserving error correction codes
#76Transaction metadata
#77Memory system, data processing system and operation method of the same
#78Storage device and operating method thereof
#79Memory system and method for operating the same
#80Data storage device performing scan operations on memory regions to move data and operation method thereof
#81Memory apparatus and data read method
#82Erroneous bit discovery in memory system
#83Memory system and operation method thereof
#84MEMORY SYSTEM AND OPERATING METHOD THEREOF
#85Apparatus and method for handling error in volatile memory of memory system based on a type of data and a state of data
#86Error correction using hierarchical decoders
#87System and methods for hardware-software cooperative pipeline error detection
#88Controller, memory system including the controller, and operating method of the memory system
#89Memory testing techniques
#90Memory system and operating method thereof
#91Memory device performing data comparison write and memory system including the same
#92Memory system and operating method of memory system
#93Determining soft data for fractional digit memory cells
#94Method and apparatus for self-diagnosis of ram error detection logic of powertrain controller
#95Device and method for generating error correction information
#96Memory system, memory module, and operation method of memory system
#97Processing of data
#98MANAGEMENT OF FAULT NOTIFICATIONS
#99Error correction management for a memory device
#100Memory error detection and correction
#101Bit block stream bit error detection method and device
#102Grouping bits of a code word for memory device operations
#103Spare substitution in memory system
#104Erroneous bit discovery in memory system
#105Detection and correction of data bit errors using error correction codes
#106Permutation of bit locations to reduce recurrence of bit error patterns in a memory device
#107Method for programming non-volatile memory
#108Memory system and operating method thereof
#109MEMORY DEVICE WITH SOFT-DECISION DECODING AND METHODS OF READING AND FORMING THEREOF
#110Memory-based distributed processor architecture
#111Memory-based distributed processor architecture
#112Memory-based distributed processor architecture
#113Memory-based distributed processor architecture
#114Memory-based distributed processor architecture
#115Memory-based distributed processor architecture
#116Error correction using hierarchical decoders
#117Transaction metadata
#118Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system
#119Inner and outer code generator for volatile memory
#120Methods and apparatuses for proactive ECC failure handling
#121Systems and methods for facilitating truly random bit generation
#122Memory system and method for operating semiconductor memory device
#123Method and device for programming non-volatile memory
#124Memory system and operating method thereof
#125Method for processing blocks of flash memory
#126Determining soft data for fractional digit memory cells
#127Bitwise sparing in a memory system
#128Modifiable stripe length in flash memory devices
#129Storage system and method of managing volumes thereof based on received correlation information of the volumes
#130In-memory data storage with adaptive memory fault tolerance
#131Memory controller and method of operating a memory controller
#132Storage device and read reclaim method thereof
#133Validation bits and offsets to represent logical pages split between data containers
#134Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system
#135Storage Device Data Access Method and Storage Device
#136Determining soft data for fractional digit memory cells
#137Data accessing method, memory storage device and memory controlling circuit unit
#138Forward error correction with configurable latency
#139Memory controller and method of reading data from nonvolatile memory by memory controller
#140Bit recovery system
#141Handling errors in ternary content addressable memories
#142Handling errors in ternary content addressable memories
#143Method and apparatus to recover from an erroneous logic state in an electronic system
#144Forward error correction with configurable latency
#145Methods and devices to increase memory device data reliability
#146Using a data ECC to detect address corruption
#147Forward error correction with configurable latency
#148Methods and devices to increase memory device data reliability
#149Forward error correction with configurable latency
#150INTERFACE DEVICE, DECODED DATA VALIDITY DETERMINATION METHOD AND RECORDING DEVICE
#151Die-to-die (D2D) interface with cyclic redundancy check (CRC) error correction capability
#152Residue-code-based error detection for cipher generation
#153Intelligent refresh of 3D NAND
#154Lutram dummy read scheme during error detection and correction
#155Selective copy-back
#156Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions