189969 ⎘
Error detection; Error correction; Monitoring; Responding to the occurrence of a fault, e.g. fault tolerance; Error detection or correction by redundancy in data representation, e.g. by using checking codes; Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK
#2Transmission failure feedback schemes for reducing crosstalk
#3MEMORY ADDRESS TRANSLATION FOR DATA PROTECTION AND RECOVERY
#4Memory cell array unit
#5Transmission failure feedback schemes for reducing crosstalk
#6System for accelerated training of bit output timings
#7Semiconductor device and semiconductor system equipped with the same
#8Memory with error correction circuit
#9Memory built-in self test error correcting code (MBIST ECC) for low voltage memories
#10Decoding scheme for error correction code structure
#11Data protection
#12Processing of data
#13Transmission failure feedback schemes for reducing crosstalk
#14Semiconductor device and semiconductor system equipped with the same
#15Error correction of multiple bit errors per codeword
#16Memory system and error correcting method of the same
#17Semiconductor device and error correction method
#18ROUTER-BASED ROUTING SELECTION
#19Configuration structure and method of a block memory
#20Dynamic cache row fail accumulation due to catastrophic failure
#21Dynamic cache row fail accumulation due to catastrophic failure
#22Stripe reconstituting method performed in storage system, method of performing garbage collection by using the stripe reconstituting method, and storage system performing the stripe reconstituting method
#23MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD
#24Memory control apparatus
#25Adjusting routing of data within a network path
#26Optimizing routing of data across a communications network
#27Codes for Enhancing the Repeated Use of Flash Memory
#28Handling errors in ternary content addressable memories
#29Handling errors in ternary content addressable memories
#30Semiconductor device and error correction method
#31Storage integrity validator
#32Implementing RAID in solid state memory
#33Data recovery on cluster failures and ECC enhancements with code word interleaving
#34Data recovery on cluster failures and ECC enhancements with code word interleaving
#35Data transmission utilizing route selection and dispersed storage error encoding
#36Redundancy schemes for non-volatile memory based on physical memory layout
#37Memory system having NAND-type flash memory and memory controller with shift read controller and threshold voltage comparison module
#38Method for providing data protection for data stored within a memory element and integrated circuit device therefor
#39Stripe-based memory operation
#40Advanced memory device having improved performance, reduced power and increased reliability
#41Advanced memory device having improved performance, reduced power and increased reliability
#42Data transmission utilizing partitioning and dispersed storage error encoding
#43Data transmission utilizing data processing and dispersed storage error encoding
#44Relaying data transmitted as encoded data slices
#45Data transmission utilizing route selection and dispersed storage error encoding
#46Systems and methods for encoding information for storage in an electronic memory and for decoding encoded information retrieved from an electronic memory
#47Solid-state storage system with parallel access of multiple flash/PCM devices
#48Stripe based memory operation
#49Implementing RAID in solid state memory
#50Advanced memory device having improved performance, reduced power and increased reliability
#51Data processing device and a method for error detection and error correction
#52Soft error protection in individual memory devices
#53Error judging circuit and shared memory system
#54Multi-state symbol error correction in matrix based codes
#55Buffer circuit for a memory module
#56Semiconductor memory device
#57Method, system, and apparatus for adjacent-symbol error correction and detection code
#58Method, system, and apparatus for adjacent-symbol error correction and detection code
#59Method, system, and apparatus for adjacent-symbol error correction and detection code
#60Soft error protection in individual memory devices
#61Partitioning data for error correction
#62Systems and methods of partitioning data to facilitate error correction
#63Systems and methods of routing data to facilitate error correction
#64Method, system, and apparatus for adjacent-symbol error correction and detection code
#65Selective sampling for data recovery
#66Low cost adjacent double error correcting code