189972 ⎘
Error detection; Error correction; Monitoring; Responding to the occurrence of a fault, e.g. fault tolerance; Error detection or correction by redundancy in data representation, e.g. by using checking codes; Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
DECODERS, DECODING METHODS, MEMORY SYSTEMS, AND MEMORY CONTROLLERS
#2ARITHMETIC CIRCUIT, MEMORY SYSTEM, AND METHOD OF CONTROLLING NONVOLATILE MEMORY
#3SYSTEMS AND METHODS FOR MEMORY RECOVERY USING SECONDARY MEMORY
#4MAC OPERATOR RELATED TO CORRECTING A COMPUTATIONAL ERROR
#5FAULT-MITIGATING METHOD AND DATA PROCESSING CIRCUIT
#6Error Correction in Computation
#7Storage system and method for using subcodes and convolutional-based LDPC interleaved coding schemes with read threshold calibration support
#8LDPC Decoder Apparatus, Device, System, Method and Computer Program
#9Residue checking of entire normalizer output of an extended result
#10Determining soft data for fractional digit memory cells
#11Error correction in computation
#12Systems and methods for mitigating faults in combinatory logic
#13Semiconductor devices and semiconductor systems including the same
#14System and methods for hardware-software cooperative pipeline error detection
#15Controller, semiconductor memory system and operating method thereof
#16Methods of sketch-based memory management and memory devices utilizing the same
#17System and method for implementing super word line zones in a memory device
#18Determining soft data for fractional digit memory cells
#19Methods for reconfiguring a storage controller when control logic fails and apparatuses using the same
#20Determining soft data for fractional digit memory cells
#21Expanded error correction codes
#22Error correction circuit for data communication providing parallelizable linear programming decoding
#23Error recover within processing stages of an integrated circuit
#24Error recovery within processing stages of an integrated circuit
#25Error recovery within processing stages of an integrated circuit
#26Modulus-based error-checking technique
#27Single event upset error detection within an integrated circuit
#28System, method and storage medium for providing segment level sparing
#29Error recovery within processing stages of an integrated circuit
#30Systematic and random error detection and recovery within processing stages of an integrated circuit
#31Preparation of qunaught states for a surface GKP code using a three (or higher) level ancilla system
#32Edge graph mapping using analog information with dynamically updated weighting factors for a surface GKP code
#33Fault-tolerant quantum error correction with a surface GKP code