ClassID:

190029

G06F11/1616 - CPC Classification

Classification description:

Error detection; Error correction; Monitoring; Responding to the occurrence of a fault, e.g. fault tolerance; Error detection or correction of the data by redundancy in hardware; Error detection by comparing the output signals of redundant hardware where the redundant component is an I/O device or an adapter therefor

Sub-classes:
Recent Application in this class:
#1
20260010442
2026-01-08

System And Method Of Drainless Link Repair For Increased Accelerator Utilization During Failure

#2
20250284602
2025-09-11

Node Anomaly Event Processing Method, Network Interface Card, and Storage Cluster

#3
20240427674
2024-12-26

Preventing loss of audio during vehicle calls when audio bus fails

#4
20240385231
2024-11-21

On-die channel impedance verification

#5
20240370341
2024-11-07

HARDWARE CONTROL PATH REDUNDANCY FOR FUNCTIONAL SAFETY OF PERIPHERALS

#6
20240143457
2024-05-02

HIGH PERFORMANCE PROCESSOR FOR LOW-WAY AND HIGH-LATENCY MEMORY INSTANCES

#7
20230185679
2023-06-15

Hardware control path redundancy for functional safety of peripherals

#8
20220276979
2022-09-01

Methods for managing communications involving a lockstep processing system

#9
20220269225
2022-08-25

Hardware control path redundancy for functional safety of peripherals

#10
20220156161
2022-05-19

MEMORY-BASED DISTRIBUTED PROCESSOR ARCHITECTURE

#11
20210365334
2021-11-25

Memory-based distributed processor architecture

#12
20210357126
2021-11-18

Active-active architecture for distributed ISCSI target in hyper-converged storage

#13
20210090617
2021-03-25

Memory-based distributed processor architecture

#14
20200250126
2020-08-06

Active-active architecture for distributed ISCSI target in hyper-converged storage

#15
20200042486
2020-02-06

Methods for managing communications involving a lockstep processing system

#16
20190341091
2019-11-07

Memory-based distributed processor architecture

#17
20190340064
2019-11-07

Memory-based distributed processor architecture

#18
20190339981
2019-11-07

Memory-based distributed processor architecture

#19
20190266055
2019-08-29

Electronic data-distribution control unit and method for operating such a control unit

#20
20190205224
2019-07-04

Replacement of storage device within IOV replication cluster connected to PCI-e switch

#21
20190179719
2019-06-13

Generating a health condition message on a health condition detected at a server to send to a host system accessing the server

#22
20190171535
2019-06-06

Data Transmission Between Computation Units Having Safe Signaling Technology

#23
20190114243
2019-04-18

Hardware lockstep checking within a fault detection interval in a system on chip

#24
20180336157
2018-11-22

Methods for managing communications involving a lockstep processing system

#25
20180322005
2018-11-08

Device and system including adaptive repair circuit

#26
20180173652
2018-06-21

Method and apparatus for data recovering during a board replacement

#27
20180107566
2018-04-19

Generating a health condition message on a health condition detected at a server to send to a host system accessing the server

#28
20180101453
2018-04-12

Implementing cable failover in multiple cable PCI express IO interconnections

#29
20180074923
2018-03-15

Implementing cable failover in multiple cable PCI Express IO interconnections

#30
20170371754
2017-12-28

Fault tolerant communication system

#31
20170315864
2017-11-02

HARDWARE-ASSISTED PROTECTION FOR SYNCHRONOUS INPUT/OUTPUT

#32
20170315860
2017-11-02

Device and system including adaptive repair circuit

#33
20170242760
2017-08-24

Monitoring device, fault-tolerant system, and control method

#34
20170116090
2017-04-27

Implementing cable failover in multiple cable PCI express IO interconnections

#35
20160179639
2016-06-23

Selectively coupling a PCI host bridge to multiple PCI communication paths

#36
20160092320
2016-03-31

Electronic fault detection unit

#37
20150363258
2015-12-17

Device and system including adaptive repair circuit

#38
20150339201
2015-11-26

Microcontroller utilizing redundant address decoders and electronic control device using the same

#39
20150127971
2015-05-07

Selectively coupling a PCI host bridge to multiple PCI communication paths

#40
20150127969
2015-05-07

Selectively coupling a PCI host bridge to multiple PCI communication paths

#41
20130019001
2013-01-17

Distributed intelligent network

#42
20090183058
2009-07-16

Communications channel interposer, method and program product for verifying integrity of untrusted subsystem responses to a request

#43
20090106430
2009-04-23

System and method for a shared I/O subsystem

#44
20080126885
2008-05-29

Fault tolerant soft error detection for storage subsystems

#45
20080109584
2008-05-08

Method and apparatus for verifying fault tolerant configuration

#46
20070162621
2007-07-12

Communications channel method for verifying integrity of untrusted subsystem responses to a request

#47
19034371
2025-09-16

Input/output system interconnect redundancy and failover

#48
15198216
2019-02-26

Method and apparatus of a profiling algorithm to quickly detect faulty disks/HBA to avoid application disruptions and higher latencies