190114 ⎘
Error detection; Error correction; Monitoring; Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing Testing of logic operation, e.g. by logic analysers
NON-INTERRUPTIVE RUN-TIME LOGIC BUILT-IN SELF-TEST FOR A MACHINE LEARNING ACCELERATOR
#2SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE, AND VEHICLE
#3ADAPTIVE BASIS SELECTION FOR ENCODED FUSION MEASUREMENTS
#4INFORMATION PROCESSING APPARATUS, INTEGRATED CIRCUIT, AND INFORMATION PROCESSING METHOD
#5System for debugging server startup sequence in debugging method applied in server
#6JTAG-based burning device
#7ADAPTIVE BASIS SELECTION FOR ENCODED FUSION MEASUREMENTS
#8Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models
#9Computer device and testing method for basic input/output system
#10Bus packet format displaying method for logic analyzer
#11Memory circuit and method of operating a memory circuit
#12Apparatuses and methods for a multiple master capable debug interface
#13Testing SoC with portable scenario models and at different levels
#14Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models
#15Vehicle control system verification device, vehicle control system, and vehicle control system verification method
#16Full memory logical erase for circuit verification
#17Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit
#18CMOS process skew sensor
#19Logic analyzer for integrated circuits
#20JTAG lockout for embedded processors in programmable devices
#21Test circuit to debug missed test clock pulses
#22Single circuit fault detection
#23Board level leakage testing for memory interface
#24Accessing a passenger transportation device control means
#25Memory circuit including overlay memory cells and method of operating thereof
#26AUTOMATIC GENERATION OF AN EXCEPTION DETECTOR FOR DETERMINING AN OVERFLOW CONDITION
#27Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models
#28Test decompressor and test method thereof
#29Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit
#30Persistent command parameter table for pre-silicon device testing
#31TEST APPARATUS, MEMORY TEST SYSTEM, AND TEST METHOD
#32Apparatuses and methods for a multiple master capable debug interface
#33Device and method for concurrently analyzing a plurality of telecommunications signal protocols
#34Semiconductor device
#35CONDITION MONITORING DEVICE AND CONDITION MONITORING METHOD FOR EXTRACTED-GAS COMPRESSION SYSTEM, AND EXTRACTED-GAS COMPRESSION SYSTEM
#36Testing SOC with portable scenario models and at different levels
#37Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models
#38Memory circuit defect correction
#39Test apparatus and testable asynchronous circuit
#40Scan compression architecture for highly compressed designs and associated methods
#41High speed functional test vectors in low power test conditions of a digital integrated circuit
#42Persistent command parameter table for pre-silicon device testing
#43Delayed authentication debug policy
#44Efficient resolution of latch race conditions in emulation
#45Apparatus and methods for logic analysis to detect trigger conditions relating to data handling transactions in systems using transaction identifiers
#46Method for error logging
#47Instruction and logic to test transactional execution status
#48Display in a graphical format of test results generated using scenario models
#49Persistent command parameter table for pre-silicon device testing
#50Power configuration verification of power-management system
#51Instruction and logic to test transactional execution status
#52Instruction and logic to test transactional execution status
#53Instruction and logic to test transactional execution status
#54Instruction and logic to test transactional execution status
#55Instruction and logic to test transactional execution status
#56Delayed authentication debug policy
#57Scan compression architecture for highly compressed designs and associated methods
#58Account state simulation service for cloud computing environments
#59Method for analyzing request logs in advance to acquire path information for identifying problematic part during operation
#60Cell library and method for designing an asynchronous integrated circuit
#61Method and device for efficient trace analysis
#62Dynamic memory cell replacement using column redundancy
#63Ultra low-power pipelined processor
#64Dual master JTAG method, circuit, and system
#65Conversion circuit and chip
#66On-chip detection of types of operations tested by an LBIST
#67On-chip detection of types of operations tested by an LBIST
#68On-die logic analyzer for semiconductor die
#69Methods and systems for testing electrical behavior of an interconnect having asymmetrical link
#70Method for identifying root cause failure in a multi-parameter self learning machine application model
#71EMBEDDED LOGIC ANALYZER
#72On-die logic analyzer for semiconductor die
#73MOTHERBOARD TEST DEVICE
#74Using central direct memory access (CDMA) controller to test integrated circuit
#75Remote testing
#76System and method for analyzing an electronics device including a logic analyzer
#77Enhanced scalable CPU for coded execution of SW in high-dependable safety relevant applications
#78Providing an on-die logic analyzer (ODLA) having reduced communications
#79System and method for testing serial ports
#80Real Time Statistical Triggers on Data Streams
#81Using central direct memory access (CDMA) controller to test integrated circuit
#82Method and apparatus of ATE IC scan test using FPGA-based system
#83On-die logic analyzer for semiconductor die
#84System and method for provisioning a vehicle interface module
#85Automated root cause identification of logic controller failure
#86System and method for provisioning a vehicle interface module
#87Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit
#88Circuitry and method to detect conditions of data
#89Protocol analyzer for consumer electronics
#90Method and system for tracing program execution in field programmable gate arrays
#91Microprocessor with trace module
#92Information transportation scheme from high functionality probe to logic analyzer
#93Model based diagnosis and repair for event logs
#94System and method for observing the behavior of an integrated circuit (IC)
#95APPARATUS AND METHOD FOR AUTOMATED TEST SETUP
#96Semiconductor integrated circuit
#97Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit
#98On demand data stream controller for programming and executing operations in an integrated circuit
#99Securing access to integrated circuit scan mode and data
#100Set top box and customer premise equipment (CPE) unit test controller
#101System and methods for reasonable functional verification of an integrated circuit design
#102Account state simulation service for cloud computing environments
#103Method and system for gathering signal states for debugging a circuit