190119 ⎘
Error detection; Error correction; Monitoring; Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing; Functional testing Reconfiguring circuits for testing, e.g. LSSD, partitioning
COMMON CONTROL AND/OR OBSERVATION FOR INTERNAL STATE TRACKING
#2SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY DEVICE
#3Automatic Host Triaging And Repair Using Structured Logging
#4NOVEL AUTOMATED FUNCTIONAL TESTING SYSTEMS AND METHODS OF MAKING AND USING THE SAME
#5LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME
#6SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
#7SYNTHETIC LOADING OF CONFIGURABLE LOGIC DEVICES
#8GENERATING AUDIT RECORDS FOR DISTRIBUTED COMPUTING SYSTEM-BASED MOTOR VEHICLE TESTS
#9METHOD AND SYSTEM FOR ESTABLISHING DATA TRANSFER PROCESSES BETWEEN COMPONENTS OF A TEST SYSTEM
#10Selectable JTAG or trace access with data store and output
#11In system test of chips in functional systems
#12SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY DEVICE
#13INFORMATION PROCESSING APPARATUS, INTEGRATED CIRCUIT, AND INFORMATION PROCESSING METHOD
#14Automated functional testing systems and methods of making and using the same
#15Dynamic prediction of system resource requirement of network software in a live network using data driven models
#16Hybrid synchronous and asynchronous control for scan-based testing
#17Synchronizing a device that has been power cycled to an already operational system
#18Automated functional testing systems and methods of making and using the same
#19Leveraging low power states for fault testing of processing cores at runtime
#20Parallel processing system runtime state reload
#21Measuring driving model coverage by microscope driving model knowledge
#22Reduced signaling interface method and apparatus
#23Machine learning for taps to accelerate TDECQ and other measurements
#24Scan testing in a processor
#25In-system test of chips in functional systems
#26Automated functional testing systems and methods of making and using the same
#27Scan synchronous-write-through testing architectures for a memory device
#28Selectable JTAG or trace access with data store and output
#29Leveraging low power states for fault testing of processing cores at runtime
#30Memory devices and methods for managing error regions
#31Automated functional testing systems and methods of making and using the same
#32Automated functional testing systems and methods of making and using the same
#33Integrated circuit with reduced signaling interface
#34Leveraging low power states for fault testing of processing cores at runtime
#35Parallel processing system runtime state reload
#36Synchronizing a device that has been power cycled to an already operational system
#37JTAG bus communication method and apparatus
#38Test methods, tester, load board and test system
#39Automated functional testing systems and methods of making and using the same
#40Device, method and system of error detection and correction in multiple devices
#41Method, system and device to test a plurality of devices by comparing test results of test chains of the plurality of devices
#42Reduced signaling interface circuit
#43Pipeline flattener with conditional triggers
#44Selectable JTAG or trace access with data store and output
#45Computer device and testing method for basic input/output system
#46Scan synchronous-write-through testing architectures for a memory device
#47Integrated circuit with JTAG port, tap linking module, and off-chip TAP interface port
#48Systems and methods for non-destructive testing online stores
#49Automated functional testing systems and methods of making and using the same
#50Test controller for concurrent testing of an application on multiple devices without using pre-recorded scripts
#51Serial data communication modes on TDI/TDO, receive TMS, send TMS
#52Apparatuses and methods including nested mode registers
#53Combinatorial serial and parallel test access port selection in a JTAG interface
#54Apparatuses and methods for a multiple master capable debug interface
#55Skew detector for data storage system
#56Reset circuit, corresponding device and method
#57Debug controller circuit
#58Operating a pipeline flattener in order to track instructions for complex
#59Operating state machine controllers after powering, decoupling, monitoring, coupling communications
#60Entering home state after soft reset signal after address match
#61Functional, tap, trace circuitry with multiplexed tap, trace data output
#62Parallel processing system runtime state reload
#63Tap, counter storing value of serial access by communication circuitry
#64Electronic device and communication method thereof
#65Combinatorial serial and parallel test access port selection in a JTAG interface
#66Signals on tap bi-directional TMS terminal selecting serial communication register
#67Scan synchronous-write-through testing architectures for a memory device
#68Serial communication interface circuit performing external loopback test and electrical device including the same
#69Apparatuses and methods including nested mode registers
#70TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs
#71Dynamic scan chain reconfiguration in an integrated circuit
#72Integrated circuit with JTAG port, TAP linking module, and off chip TAP interface port
#73Trace domain controller with test data I/O/control, internal control I/O
#74Semiconductor integrated circuit and semiconductor integrated circuit diagnosis method
#75Methods for updating memory maps of a system-on-chip
#76Address/instruction registers, target domain interfaces, control information controlling all domains
#77Internal circuit TMS input, FIFO coupled to parallel-input serial-output register
#78TMS pin for mode signal and output for read data
#79Semiconductor device and scan test method including writing and reading test data
#80Taps with TO-T2, T4 classes with, without topology selection logic
#81Monitoring communication link in powered-up device for synchronization point sequence
#82Apparatuses and methods for a multiple master capable debug interface
#83One tap domain coupling two trace circuits, address command port
#84In-memory data storage with adaptive memory fault tolerance
#85Selectively uncoupling tap and coupling OCI responsive to link instruction
#86Selective loading of components within a node to speed up maintenance actions
#87Addressable tap domain selection circuit with instruction and linking circuits
#88TCK, TMS(C) clock, gating circuitry providing selection and deselection outputs
#89Taps of different scan classes with, without topology selection logic
#90TMS serial communication circuitry coupled to tap IR enable output
#91Operating a pipeline flattener in order to track instructions for complex breakpoints
#92Embedded universal serial bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems
#93TCK/TMS(C) counter circuitry with third, fourth count and reset outputs
#94SCALABLE METHOD AND APPARATUS TO CONFIGURE A LINK
#95Off-chip tap interface control with instruction register, multiplexer and buffer
#96TAP addressable circuit with bi-directional TMS and second signal lead
#97Debug architecture
#98Method for managing the operation of a circuit with triple modular redundancy and associated device
#99Bi-directional TCK lead carrying TCK and frame data in/out signal
#100CLK/TMS counter having reset output coupled to fourth count output
#101System and method for testing computing hardware in computer rack
#102System and method for automated functional coverage generation and management for IC design protocols
#103Class T0-T2 and T4 TAPS with, without topology selection logic
#104Target system recognizing synchronization point sequence on mode select input
#105Tap, data input, output circuitry coupled to mode select lead
#106Test, validation, and debug architecture
#107Operating two tap system after detecting shared bus synchronization sequence
#108Linking circuitry selectively coupling TDI/TDO with first and second domains
#109IC gating selection on first/second and deselection on second/third counts
#110I/O circuitry free of test clock coupled with destination/source circuitry
#111Dual master JTAG method, circuit, and system
#112System and method to design and test a yield sensitive circuit
#113Linking circuitry for IC TAP, core TAP, off-chip TAP interface
#114Multi-core device, test device, and method of diagnosing failure
#115Systems and methods for non-destructive testing online stores
#116Asynchronous programmable JTAG-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic
#117System and method of emulating multiple custom prototype boards
#118Test access port and TMS communication circuitry with state machines
#119Method for JTAG-driven remote scanning
#120PSMI using at-speed scan capture
#121Processor maintaining reset-state after reset signal is suspended
#122Adapter power up circuitry forcing tap states and decoupling tap
#123Debug architecture
#124Debug architecture
#125Remote boundary scanning
#126Method and apparatus for output of high-bandwidth debug data/traces in ICS and SoCs using embedded high speed debug
#127Test access system, method and computer-accessible medium for chips with spare identical cores
#128USB device and detection method thereof
#129Debugging device and method for performing a debugging process to a target system
#130Controller, storage apparatus, method of testing storage apparatus, and computer-readable storage medium
#131Adapter circuitry resetting scan test logic to mandatory feature set
#132Apparatus for JTAG-driven remote scanning
#133MAPPING CIRCUIT TEST LOGIC BY ANALYZING REGISTER TRANSFER LEVEL CIRCUIT MODELS
#134Packetizing JTAG across industry standard interfaces
#135Method of testing a device under test, device under test, and semiconductor test system including the device under test
#136Operating a pipeline flattener in order to track instructions for complex breakpoints
#137Scalable method and apparatus to configure a link
#138Circuit arrangement and method for testing same
#139TESTING MEMORY SUBSYSTEM CONNECTIVITY
#140Address and command port connecting trace circuitry and TAP domain
#141Efficient wrapper cell design for scan testing of integrated
#142Advanced/enhanced protocol circuitry connected to TCK, TMS, and topology circuitry
#143Voter tester for redundant systems
#144System-on-chip with master/slave debug interface
#145Thread selection for multithreaded processing
#146Adapter and scan test logic synchronizing from idle state
#147Functional fabric based test wrapper for circuit testing of IP blocks
#148Functional fabric-based test controller for functional and structural test and debug
#149Bi-directional TMS lead carrying TMS and frame data in/out signals
#150Address and instruction controller with TCK, TMS, address match inputs
#151Compound hold-time fault diagnosis
#152SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
#153Integrated circuit testing
#154Debug state machines and methods of their operation
#155Selecting on die test port and off die interface leads
#156Micro controller, driving method thereof and display device using the same
#157Method for debugging reconfigurable architectures
#158Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations
#159Adaptor detecting sequence on TMS and coupling TAP to TCK
#160Die selectively connecting TAP leads to second die
#161Synchronizing remote devices with synchronization sequence on JTAG control lead
#162Communication of a diagnostic signal and a functional signal by an integrated circuit
#163Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit
#164Data processing apparatus and method for testing a circuit block using scan chains
#165Test mode soft reset circuitry and methods
#166Sequential digital circuitry with test scan
#167Inverter and TMS clocked flip-flop pairs between TCK and reset
#168Error controlling system, processor and error injection method
#169Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit
#170Processing system hardware diagnostics
#171METHOD FOR INSERTING TEST POINTS FOR LOGIC CIRCUITS AND LOGIC CIRCUIT TESTING APPARATUS
#172Source and destination data circuitry coupled to bi-directional TMS lead
#173Reduced signaling interface method and apparatus
#174Communication between controller and addressed target devices over data signal
#175System-on-chip with master/slave debug interface
#176TAP interface outputs connected to TAP interface inputs
#177Non-volatile memory system with self test capability
#178Integrated circuit having secure access to test modes
#179Compactor independent direct diagnosis of test hardware
#180Selectable JTAG or trace access with data store and output
#181JTAG bus communication method and apparatus
#182Circuit and method providing dynamic scan chain partitioning
#183Scalable method and apparatus for link with reconfigurable ports
#184SYSTEM AND METHOD FOR TESTING APPLICATION-SPECIFIC BLOCKS EMBEDDED IN RECONFIGURABLE ARRAYS
#185Voter tester for redundant systems
#186Integrated circuit with JTAG port, tap linking module, and off-chip tap interface port
#187Reduced signaling interface method and apparatus
#188Processor to JTAG test access port interface
#189Test access port
#190Automatic scan format selection based on scan topology selection
#191Selecting a scan topology
#192Series equivalent scans across multiple scan topologies
#193Ascertaining configuration by storing data signals in a topology register
#194Dynamic broadcast of configuration loads supporting multiple transfer formats
#195Alternate Signaling Mechanism Using Clock and Data
#196Bus failure management method and system
#197Selectable JTAG or trace access with data store and output
#198AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns
#199Test mode soft reset circuitry and methods
#200System and method for input/output characterization
#201System-on-chip with master/slave debug interface
#202In system diagnostics through scan matrix
#203Maintaining data coherency in multi-clock systems
#204Method of testing memory array at operational speed using scan
#205Method for debugging reconfigurable architectures
#206Method and apparatus for describing and testing a system-on-chip
#207Method and apparatus for describing parallel access to a system-on-chip
#208Local and global address compare with tap interface TDI/TDO lead
#209Distributed test compression for integrated circuits
#210JTAG bus communication method and apparatus
#211Enhancing speed of simulation of an IC design while testing scan circuitry
#212Self-resetting, self-correcting latches
#213Method for debugging reconfigurable architectures
#214Powering up adapter and scan test logic TAP controllers
#215Synchronizing TAP controllers with sequence on TMS lead
#216Method and apparatus for soft-error immune and self-correcting latches
#217Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit
#218Communications System for Implementation of Synchronous, Multichannel, Galvanically Isolated Instrumentation Devices
#219Fault recovery on a massively parallel computer system to handle node failures without ending an executing job
#220Communication of a diagnostic signal and a functional signal by an integrated circuit
#221Integrated circuit with JTAG port, TAP linking module, and off-chip TAP interface port
#222SINGLE PCI CARD IMPLEMENTATION OF DEVELOPMENT SYSTEM CONTROLLER, LAB INSTRUMENT CONTROLLER, AND JTAG DEBUGGER
#223Scan Testing Interface
#224JTAG to system bus interface for accessing embedded analysis instruments
#225Integrated circuit having a subordinate test interface
#226JTAG circuit transferring data between devices on TCK terminals
#227Generating scan test vectors for proprietary cores using pseudo pins
#228Compactor independent fault diagnosis
#229Method and apparatus for soft-error immune and self-correcting latches
#230Non-volatile memory system with self test capability
#231Selectable JTAG or trace access with data store and output
#232Self-resetting, self-correcting latches
#233Methods and apparatus for interfacing between test system and memory
#234Microcomputer and method for developing system program
#235Test access port
#236Device including a field having function cells and information providing cells controlled by the function cells
#237Electronic circuit device
#238Encrypted JTAG interface
#239Electronic circuit device
#240Addressing error and address detection systems and methods
#241Addressable tap domain selection circuit with TDI/TDO external terminal
#242Method and system of using a single EJTAG interface for multiple tap controllers
#243Device and method for debugging embedded system
#244Apparatus for developing and verifying system-on-chip for internet phone
#245Compactor independent direct diagnosis of test hardware
#246Leakage current reduction system and method
#247Processor condition sensing circuits, systems and methods
#248System and method for remotely configuring semiconductor functional circuits
#249Method and apparatus for interfacing between test system and embedded memory on test mode setting operation
#250System and method for testing and configuring semiconductor functional circuits
#251Integrated circuit configuration system and method
#252System and method for configuring semiconductor functional circuits
#253System and method for increasing die yield
#254Multicore processor test method
#255Compactor independent fault diagnosis
#256Testing memory access signal connections
#257System and method for debugging system-on-chips
#258Programme-controlled unit with crossbar employing a diagnostic port
#259JTAG circuit transferring data between devices on TMS terminals
#260Microcomputer And Method For Debugging Microcomputer
#261IC with JTAG port, linking module, and off-chip TAP interface
#262System, method and software for isolating dual-channel memory during diagnostics
#263Method for debugging reconfigurable architectures
#264Modifying scan patterns to enable broadcasting a scan enable signal to multiple circuit blocks
#265Systems and methods for scan chain stitching
#266Redundant segment for efficient in-service testing
#267Method and device for generating boundary-scan interconnection lines
#268Method and system for generating a validation test
#269Multiple reset types in a system
#270Sharing a JTAG interface among multiple partitions
#271Methods for updating memory maps of a system-on-chip
#272Methods and apparatus for high-speed serial interface link assist
#273Skew detector for data storage system
#274Performance screen ring oscillator formed from multi-dimensional pairings of scan chains
#275Simulation that transfers port values of a design block via a configuration block of a programmable device