190254 ⎘
Accessing, addressing or allocating within memory systems or architectures; Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems; Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches; Multiple simultaneous or quasi-simultaneous cache accessing; Cache with multiple tag or data arrays being simultaneously accessible Cache with interleaved addressing
FRAMEWORK FOR DRAM TO PHYSICAL ADDRESS CONVERSION
#2SHADOW TAG MANAGEMENT FOR ACCELERATOR PARTITIONS
#3DELAYED SNOOP FOR MULTI-CACHE SYSTEMS
#4MULTICORE SHARED CACHE OPERATION ENGINE
#5CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#6VIRTUAL NETWORK PRE-ARBITRATION
#7MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
#8MULTICORE SHARED CACHE OPERATION ENGINE
#9TECHNIQUES FOR STORING DATA AND TAGS IN DIFFERENT MEMORY ARRAYS
#10CONFIGURABLE CACHE FOR COHERENT SYSTEM
#11METHOD AND APPARATUS FOR USING A STORAGE SYSTEM AS MAIN MEMORY
#12MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
#13Enhanced write performance utilizing program interleave
#14DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THREAD PERFORMANCE
#15Multicore shared cache operation engine
#16Techniques for storing data and tags in different memory arrays
#17Configurable cache for coherent system
#18Enhanced write performance utilizing program interleave
#19Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#20Method and apparatus for using a storage system as main memory
#21Memory system executing background operation using external device and operation method thereof
#22MEMORY INTERLEAVING COORDINATED BY NETWORKED PROCESSING UNITS
#23Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#24Multicore, multibank, fully concurrent coherence controller
#25CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#26Look-up table containing processor-in-memory cluster for data-intensive applications
#27DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
#28Memory system and operating method thereof
#29APPARATUS AND METHOD FOR IMPROVING INPUT/OUTPUT THROUGHPUT OF MEMORY SYSTEM
#30Configurable cache for multi-endpoint heterogeneous coherent system
#31Delayed snoop for improved multi-process false sharing parallel thread performance
#32Multicore shared cache operation engine
#33Memory architecture for efficient spatial-temporal data storage and access
#34Dynamic memory address encoding
#35Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#36Multi-processor bridge with cache allocate awareness
#37MULTICORE SHARED CACHE OPERATION ENGINE
#38Method and apparatus for using a storage system as main memory
#39Memory architecture for efficient spatial-temporal data storage and access
#40Dynamic memory address encoding
#41Memory Interleaving Method and Apparatus
#42Memory system and operating method thereof
#43Address interleaving for machine learning
#44Techniques for storing data and tags in different memory arrays
#45Apparatus and method for improving input/output throughput of memory system
#46Multiple virtual NUMA domains within a single NUMA domain via operating system interface tables
#47Operating method forcing the second operation to fail using a scatter-gather buffer and memory system thereof
#48Adaptive cache reconfiguration via clustering
#49Distributed error detection and correction with hamming code handoff
#50Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect
#51Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#52Credit aware central arbitration for multi-endpoint, multi-core system
#53Multicore, multibank, fully concurrent coherence controller
#54Delayed snoop for improved multi-process false sharing parallel thread performance
#55Configurable cache for multi-endpoint heterogeneous coherent system
#56Method and apparatus for using a storage system as main memory
#57Bits register for synonyms in a memory system
#58Delayed write-back in memory
#59Apparatuses and methods for determining efficient memory partitioning
#60Bits register for synonyms in a memory system
#61Bits register for synonyms in a memory system
#62Memory with reduced exposure to manufacturing related data corruption errors
#63Data storage device and operating method thereof
#64Interleaved cache controllers with shared metadata and related devices and systems
#65Delayed write-back in memory
#66Method for increasing cache size
#67Memory partitioning for a computing system with memory pools
#68Safe write-back cache replicating only dirty data
#69PERFORMING DISTRIBUTED BRANCH PREDICTION USING FUSED PROCESSOR CORES IN PROCESSOR-BASED SYSTEMS
#70Selevtive application of interleave based on type of data to be stored in memory
#71Computing apparatuses and methods of processing operations thereof
#72Create page locality in cache controller cache allocation
#73Method for increasing cache size
#74System including hierarchical memory modules having different types of integrated circuit memory devices
#75INTERLEAVED CACHE CONTROLLERS WITH SHARED METADATA AND RELATED DEVICES AND SYSTEMS
#76Techniques for storing data and tags in different memory arrays
#77Method for increasing cache size
#78System including hierarchical memory modules having different types of integrated circuit memory devices
#79Create page locality in cache controller cache allocation
#80Memory management method and apparatus
#81Methods of selecting available cache in multiple cluster system
#82Data processing system having combined memory block and stack package
#83Hierarchical memory system compiler
#84System including hierarchical memory modules having different types of integrated circuit memory devices
#85ELECTRONIC DEVICE, AND METHOD FOR ACCESSING DATA IN ELECTRONIC DEVICE
#86Storage system having tag storage device with multiple tag entries associated with same data storage line for data recycling and related tag storage device
#87Memory hierarchy using row-based compression
#88Address generating circuit and address generating method
#89Cache prefetch for NFA instructions
#90Decoded picture buffer size management
#91Memory system and SoC including linear addresss remapping logic
#92APPARATUS AND METHOD FOR TESTING A CACHE MEMORY
#93ACCELERATED INTERLEAVED MEMORY DATA TRANSFERS IN MICROPROCESSOR-BASED SYSTEMS, AND RELATED DEVICES, METHODS, AND COMPUTER-READABLE MEDIA
#94Techniques for storing data and tags in different memory arrays
#95Multi-bank cache memory
#96System and method for storing data in a virtualized high speed memory system with an integrated memory mapping table
#97System and method for increasing cache size
#98Dynamically altering a pipeline controller mode based on resource availability
#99Dynamically supporting variable cache array busy and access times for a targeted interleave
#100Update Handler For Multi-Channel Cache
#101Cache system
#102System and method for storing data in a virtualized high speed memory system
#103Method and system for achieving die parallelism through block interleaving
#104System and method of increasing cache size
#105METHOD AND APPARATUS FOR COMBINING INDEPENDENT DATA CACHES
#106System including hierarchical memory modules having different types of integrated circuit memory devices
#107CACHE MEMORY DEVICE
#108MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME
#109Storage system that prioritizes storage requests
#110L2 cache controller with slice directory and unified cache structure
#111Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing
#112System bus structure for large L2 cache array topology with different latency domains
#113System bus structure for large L2 cache array topology with different latency domains
#114System and method for programmable bank selection for banked memory subsystems
#115Multi-port high-level cache unit and a method for retrieving information from a multi-port high-level cache unit
#116Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels
#117Cache with high access store bandwidth
#118Memory arrangement for multi-processor systems including a memory queue
#119Multiple independent coherence planes for maintaining coherency
#120Cache organization for power optimized memory access
#121Banked cache with multiplexer
#122Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory
#123Method and apparatus for performing data prefetch in a multiprocessor system
#124Half-good mode for large L2 cache array topology with different latency domains
#125L2 cache controller with slice directory and unified cache structure
#126System bus structure for large L2 cache array topology with different latency domains
#127Methods and apparatus for dynamically managing banked memory
#128Multiport cache memory which reduces probability of bank contention and access control system thereof
#129Banking render cache for multiple access
#130Instruction cache and method for reducing memory conflicts
#131Adaptive layout cache organization to enable optimal cache hardware performance
#132Processor and processor method of operation
#133Interleave pre-checking in front of shared caches with pipelined access
#134Shadow tag management for accelerator partitions
#135Transparent interleaving of compressed cache lines
#136Dataset paging cache for storage system