190267 ⎘
Accessing, addressing or allocating within memory systems or architectures; Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems; Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches; Cache access modes Burst mode
MEMORY CONTROLLER HAVING A WRITE BUFFERS
#2SPLIT-ENTRY DRAM CACHE
#3HANDLING NON-CORRECTABLE ERRORS
#4DATA BURST QUEUE MANAGEMENT
#5BANDWIDTH BOOSTED STACKED MEMORY
#6METHOD AND SYSTEM FOR IN-LINE ECC PROTECTION
#7PARALLELIZED SCRUBBING TRANSACTIONS
#8HANDLING NON-CORRECTABLE ERRORS
#9STORAGE MODULE SUPPORTING SINGLE SERIALIZED WRITE INTERFACING SCHEME AND OPERATION METHOD THEREOF
#10Method and system for in-line ECC protection
#11ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER
#12Data burst queue management
#13Parallelized scrubbing transactions
#14METHOD AND DEVICE FOR RAPIDLY SEARCHING CACHE
#15Bandwidth boosted stacked memory
#16Handling non-correctable errors
#17Using a second content-addressable memory to manage memory burst accesses in memory sub-systems
#18Method and apparatus for cache slot allocation based on data origination location or final data destination location
#19Error correcting codes for multi-master memory controller
#20MEMORY SYSTEM OF AN ARTIFICIAL NEURAL NETWORK BASED ON A DATA LOCALITY OF AN ARTIFICIAL NEURAL NETWORK
#21Cache line data
#22Method and system for in-line ECC protection
#23Method and apparatus for cache slot allocation based on data origination location or final data destination location
#24Semiconductor apparatus and readout method
#25Dynamic random access memory (DRAM) with scalable meta data
#26STAGING BUFFER ARBITRATION
#27Memory striping approach that interleaves sub protected data words
#28METHOD OF DEFENDING AGAINST MEMORY SHARING-BASED SIDE-CHANNEL ATTACKS BY EMBEDDING RANDOM VALUE IN BINARIES
#29Bandwidth boosted stacked memory
#30Adjusting characteristic of system based on profile
#31Processing data in memory using an FPGA
#32Handling non-correctable errors
#33Error correcting codes for multi-master memory controller
#34Parallelized scrubbing transactions
#35Bandwidth boosted stacked memory
#36Semiconductor apparatus and semiconductor system including the semiconductor apparatus
#37Memory rank design for a memory channel that is optimized for graph applications
#38DATA CACHING DEVICE AND CONTROL METHOD THEREFOR, DATA PROCESSING CHIP, AND DATA PROCESSING SYSTEM
#39Using a second content-addressable memory to manage memory burst accesses in memory sub-systems
#40Method and system for in-line ECC protection
#41Nonvolatile memory capable of outputting data using wraparound scheme, computing system having the same, and read method thereof
#42Method using logical based addressing for latency reduction
#43Methods and systems for accessing a memory
#44Magnetic random access memory with dynamic random access memory (DRAM)-like interface
#45Managing flash memory read operations
#46Method using logical based addressing for latency reduction
#47BURST LENGTH DEFINED PAGE SIZE AND RELATED METHODS
#48Cache line data
#49Method and device for cache management
#50Memory with reduced exposure to manufacturing related data corruption errors
#51Device and method for enhancing item access bandwidth and atomic operation
#52Locking a cache line for write operations on a bus
#53Memory device and memory system including the same
#54Magnetic random access memory with dynamic random access memory (DRAM)-like interface
#55Index based memory access using single instruction multiple data unit
#56Memory move instruction sequence targeting an accelerator switchboard
#57Memory move instruction sequence including a stream of copy-type and paste-type instructions
#58System and method for operating a DRR-compatible asynchronous memory module
#59Apparatus having cache memory disposed in a memory transaction path between interconnect circuitry and a non-volatile memory, and corresponding method
#60Magnetic random access memory with dynamic random access memory (DRAM)-like interface
#61Nonvolatile memory capable of outputting data using wraparound scheme, computing system having the same, and read method thereof
#62Word line auto-booting in a spin-torque magnetic memery having local source lines
#63Automated latency monitoring
#64Efficiently generating selection masks for row selections within indexed address spaces
#65Advance cache allocator
#66Locking a cache line for write operations on a bus
#67Magnetic random access memory with dynamic random access memory (DRAM)-like interface
#68Word line auto-booting in a spin-torque magnetic memory having local source lines
#69Magnetic random access memory with dynamic random access memory (DRAM)-like interface
#70Arithmetic processing device, information processing device, and control method of arithmetic processing device
#71Burst length defined page size
#72Data transmission circuit and data transmission method using configurable threshold and related universal serial bus system
#73Data structure product and method for interface transmission
#74DRAM cache with tags and data jointly stored in physical rows
#75Magnetic random access memory with dynamic random access memory (DRAM)-like interface
#76Locking a cache line for write operations on a bus
#77Methods and apparatus for burst data transfers between double data rate (DDR) memories and embedded processors during training
#78Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
#79Processing unit, chip, computing device and method for accelerating data transmission
#80BUFFER MEMORY DEVICE, MEMORY SYSTEM, AND DATA TRANSFER METHOD
#81BUFFER MEMORY DEVICE, MEMORY SYSTEM, AND DATA READING METHOD
#82Burst-based cache dead block prediction
#83Device for real-time streaming of two or more streams in parallel to a solid state memory device array
#84APPARATUS AND METHOD FOR LOADING AND STORING MULTI-DIMENSIONAL ARRAYS OF DATA IN A PARALLEL PROCESSING UNIT
#85System and method for facilitating operation of an input/output link
#86System and method for fetching information to a cache module using a write back allocate algorithm
#87DATA PROCESSING CIRCUIT, CACHE SYSTEM, AND DATA TRANSFER APPARATUS
#88Cache memory capable of adjusting burst length of write-back data in write-back operation
#89System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
#90Methods and apparatuses for flushing write-combined data from a buffer
#91METHOD AND APPARATUS FOR MEMORY COMPRESSION
#92Random cache line refill
#93SCANNER CONTROLLER
#94Systems and methods for remote direct memory access to processor caches for RDMA reads and writes
#95Direct cache access in multiple core processors
#96Method and system for data packer unit for accelerating stack functions
#97Performing direct cache access transactions based on a memory access data structure
#98Device and method for configuring a cache tag in accordance with burst length
#99Method and device for burst reading/writing memory data
#100Drawing apparatus, drawing method, drawing program and drawing integrated circuit
#101Integrated circuit including a memory having low initial latency
#102Matching memory transactions to cache line boundaries
#103Methodology and apparatus for implementing write combining
#104Apparatus and method for providing information to a cache module using fetch bursts
#105Method and apparatus for memory compression
#106Cache line memory and method therefor
#107Device and method for configuring a cache tag in accordance with burst length
#108Method for supporting improved burst transfers on a coherent bus
#109Burst mode implementation in a memory device
#110High speed memory system
#111Buffer page roll implementation for PCI-X block read transactions
#112Processor with reduced interrupt latency
#113Tensor data distribution using grid direct-memory access (DMA) controller
#114Methods and systems for processing read and write requests