MANAGING DATA USING PERSISTENT STORAGE

METHOD, DEVICE, AND COMPUTER PROGRAM PRODUCT FOR CACHING

Managing data using persistent storage

Slot/sub-slot prefetch architecture for multiple memory requestors

Disassociating memory units with a host system

Data cache region prefetcher

Effective PCIe utilization by PCIe TLP coalescing

Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments

Cryptographic system memory management

Disassociating memory units with a host system

Slot/sub-slot prefetch architecture for multiple memory requestors

METHOD FOR IMPLEMENTING A LINE SPEED INTERCONNECT STRUCTURE

MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPRESSED CACHE LINES

Computing system and method using bit counter

Cryptographic system memory management

Computing system and method using bit counter

Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments

Slot/sub-slot prefetch architecture for multiple memory requestors

DATA READING METHOD BASED ON VARIABLE CACHE LINE

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

System, apparatus and method for selective enabling of locality-based instruction handling

Method for managing transactions routing between source equipment and target equipment

Systems and methods for performing memory compression

Method for implementing a line speed interconnect structure

High-bandwidth prefetcher for high-bandwidth memory

Compressed pages having data and compression metadata

System, apparatus and method for multi-cacheline small object memory tagging

Information processing method and device, and method and device for displaying dynamic information

Multi-level system memory with near memory capable of storing compressed cache lines

Computing system, and driving method and compiling method thereof

HIGH-BANDWIDTH PREFETCHER FOR HIGH-BANDWIDTH MEMORY

System, apparatus and method for selective enabling of locality-based instruction handling

Dynamically selecting a memory boundary to be used in performing operations

Slot/sub-slot prefetch architecture for multiple memory requestors

Method for implementing a line speed interconnect structure

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

Cryptographic system memory management

Method and device for managing caches

Computing apparatuses and methods of processing operations thereof

Synchronous input/output (I/O) cache line padding

PERFORMANCE-DRIVEN CACHE LINE MEMORY ACCESS

Reducing memory access bandwidth based on prediction of memory request size

Cache device and semiconductor device including a tag memory storing absence, compression and write state information

Memory integrity with error detection and correction

Computer-program products and methods for annotating ambiguous terms of electronic text documents

CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM

Memory management method and apparatus

Cache line compaction of compressed data segments

Resolving memory accesses crossing cache line boundaries

Apparatus and method for considering spatial locality in loading data elements for execution

Power aware padding

Supplemental write cache command for bandwidth compression

Cache line compaction of compressed data segments

Electronic device with cache memory and method of operating the same

System and method for dictionary-based cache-line level code compression for on-chip memories using gradual bit removal

Memory module and system supporting parallel and serial access modes

Computer processor employing double-ended instruction decoding

Storage system having data storage lines with different data storage line sizes

System and methods for caching a small size I/O to improve caching device endurance

Memory system controller including a multi-resolution internal cache

Systems, computer-program products and methods for annotating documents by expanding abbreviated text

Computer-program products and methods for annotating ambiguous terms of electronic text documents

Storage system having tag storage device with multiple tag entries associated with same data storage line for data recycling and related tag storage device

Hardware managed compressed cache

Electronic circuit for fitting a virtual address range to a physical memory containing faulty address

Method and system for automatic space organization in tier2 solid state drive (SSD) cache in databases for multi page support

Image optimized rolling cache system

Hardware managed compressed cache

Instruction boundary prediction for variable length instruction set

Update mask for handling interaction between fills and updates

Hybrid cache

Cache memory system and method using dynamically allocated dirty mask space

Performance-driven cache line memory access

Performance-driven cache line memory access

Methods and apparatus for managing page crossing instructions with different cacheability

Fetch width predictor

Techniques to request stored data from a memory

Non-disruptive controller replacement in network storage systems

Method and apparatus for a partial-address select-signal generator with address shift

Cache system and a method of operating a cache memory

Method and apparatus for tracking extra data permissions in an instruction cache

Method and system for managing power grid data

Configurable multirank memory system with interface circuit

Processor for performing operations with two wide operands

Parallel processing of two-dimensional data, storage of plural data of the processing results in a cache line and transfer of the data to a memory as in the cache line

Cache line allocation method and system

Processor architecture for executing wide transform slice instructions

Opcode length caching

Fast unaligned cache access system and method

Memory controller with automatic error detection and correction

Prefetcher with arbitrary downstream prefetch cancelation

Double-buffered data storage to reduce prefetch generation stalls

Speculation-aware memory controller arbiter

Prefetch address hit prediction to reduce memory access latency

Prefetch stream filter with FIFO allocation and stream direction prediction

Slot/sub-slot prefetch architecture for multiple memory requestors

Variable line size prefetcher for multiple memory requestors

PROCESSOR, APPARATUS, AND METHOD FOR MEMORY MANAGEMENT

Cache system

Processor Architecture for Executing Wide Transform Slice Instructions

High performance unaligned cache access

Adaptive linesize in a cache

Dynamic runtime modification of array layout for offset

Loading data to vector renamed register from across multiple cache lines

High availability memory system

Multiple Cache Line Size

Compressed cache controller valid word status using pointers

System and method for high performance synchronous DRAM memory controller

SET ASSOCIATIVE CACHE APPARATUS, SET ASSOCIATIVE CACHE METHOD AND PROCESSOR SYSTEM

Data processing system and cache control method

Instruction cache system, instruction-cache-system control method, and information processing apparatus

Adaptive buffer device and method thereof

Transaction manager and cache for processing agent

Partial cache line accesses based on memory access patterns

Dynamic selection of a memory access size

Interconnect operation indicating acceptability of partial data delivery

Cache management for partial cache line operations

Dynamic data type aligned cache optimized for misaligned packed structures

Integration of secure data transfer applications for generic IO devices

Contiguously packed data

Storage control device, and control method for storage control device

System and article of manufacture for using a reentry data stet to decode compressed data

Data cache architecture and cache algorithm used therein

Processor architecture for executing wide transform slice instructions

Processor for executing extract controlled by a register instruction

Cache memory device and microprocessor

Processor architecture for executing transfers between wide operand memories

Adaptive Caching of Input / Output Data

Cache memory

Cache memory

System and program for using a reentry data set to decode compressed data

Cache architecture for a processing unit providing reduced power consumption in cache operation

Multi-port integrated cache

APPARATUS AND METHOD FOR FILTERING UNUSED SUB-BLOCKS IN CACHE MEMORIES

Storage system and method of controlling a storage system

Apparatus, system, and method for efficient adaptive parallel data clustering for loading data into a table

System and program product for error recovery while decoding cached compressed data

System and program product for error recovery while decoding cached compressed data

DATA TRANSFER APPARATUS

Method and arrangement for cache memory management, related processor architecture

Method and apparatus for efficiently accessing both aligned and unaligned data from a memory

Systems and methods for providing data modification operations in memory subsystems

Mechanism that provides efficient multi-word load atomicity

Method and apparatus for caching variable length instructions

Multi-portioned instruction memory

Command processing apparatus and command processing method

Storage control device, and control method for storage control device

Method and system for symmetric allocation for a shared L2 mapping cache

Cache memory and its controlling method

Method and apparatus for accessing misaligned data streams

Memory apparatus and memory control method

Microprocessor apparatus and method for enabling variable width data transfers

Adaptive input / output compressed system and data cache and system using same

Cache memory device and microprocessor

Handling cache miss in an instruction crossing a cache line boundary

Method and apparatus for storing compressed code without an index table

Systems and methods for enabling communications among devices in a multi-cache line size environment and disabling communications among devices of incompatible cache line sizes

Method and apparatus for efficiently accessing both aligned and unaligned data from a memory

System and method for cache coherency in a cache with different cache location lengths

Mechanism that provides efficient multi-word load atomicity

Apparatus and method for filtering unused sub-blocks in cache memories

Cache memory system and control method of the cache memory system

Cache memory system and method capable of adaptively accommodating various memory line sizes

Method for using a reentry data set to decode compressed data

Selectively changeable line width memory

Efficient data cache

L0 cache alignment circuit

Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data

Fast unaligned cache access system and method

Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system

Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information

Mechanism to increase data compression in a cache

Mechanism to compress data in a cache

Methods and systems for managing persistent storage of small data objects

Method, system, and program product for error recovery while transmitting and decoding compressed data

Method, system, and program product of error recovery while decoding cached compressed data

Method, device, and computer program product for caching

Compression format designed for a very fast decompressor

Cache management in a mobile device