190292 ⎘
Accessing, addressing or allocating within memory systems or architectures; Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems; Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being generated by decoding an array or storage
ENCODED HOST TO DLA TRAFFIC
#2APPLICATION CACHING OPTIMIZATION AND SYNCHRONIZATION
#3Semiconductor memory device including unit page buffer blocks having four page buffer pairs
#4Bit level sharding of sensitive data for increased security
#5Host device performing near data processing function and accelerator system including the same
#6Encoded host to DLA traffic
#7Method and system for biological information pattern storage and readout
#8Combined transparent/non-transparent cache
#9Storing arrays of data in data processing systems
#10Combined transparent/non-transparent cache
#11Address collision avoidance in a memory device
#12Managing storage of digital content
#13MRU batching to reduce lock contention
#14Combined transparent/non-transparent cache
#15System and method for supporting a low contention queue in a distributed data grid
#16Combined transparent/non-transparent cache
#17Serial configuration of a reconfigurable instruction cell array
#18Balanced P-LRU tree for a “multiple of 3” number of ways cache
#19Combined transparent/non-transparent cache
#20Combined transparent/non-transparent cache
#21Combined transparent/non-transparent cache
#22Pseudo-LRU cache line replacement for a high-speed cache
#23Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation
#24Method for updating information used for selecting candidate in LRU control
#25Pseudo-LRU virtual counter for a locking cache
#26Cache device and method for determining LRU identifier by pointer values
#27Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class
#28Method for software controllable dynamically lockable cache line replacement system
#29Pseudo-LRU for a locking cache
#30System, apparatus, and method of cache management