190316 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
Sub-classes:PROCESSOR FOR CONFIGURABLE PARALLEL COMPUTATIONS
#2DYNAMIC CONTROL DEVICE AND DYNAMIC CONTROL METHOD
#3DELAYED SNOOP FOR MULTI-CACHE SYSTEMS
#4MULTICORE SHARED CACHE OPERATION ENGINE
#5CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#6VIRTUAL NETWORK PRE-ARBITRATION
#7SHARED CONDUCTOR FOR SIGNALS DIFFERING IN FREQUENCY
#8MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
#9PROCESSOR IDENTIFICATION
#10BANK TO BANK DATA TRANSFER
#11MULTICORE SHARED CACHE OPERATION ENGINE
#12CONFIGURING PCI EXPRESS MODULE USING HARDWARE IN A MEMORY SUB-SYSTEM
#13CONFIGURABLE CACHE FOR COHERENT SYSTEM
#14MEMORY CHIP HAVING AN INTEGRATED DATA MOVER
#15CIRCUIT ARCHITECTURE MAPPING SIGNALS TO FUNCTIONS FOR STATE MACHINE EXECUTION
#16HYBRID MICROPROCESSOR AND PROGRAMMABLE LOGIC DEVICE (PLD)-BASED ARCHITECTURE INCLUDING INTER PROCESSOR COMMUNICATION
#17DUAL CONNECTION PERIPHERAL DEVICE WITH CAPTIVE CABLE AND AUXILIARY PORT
#18MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
#19SYSTEMS AND METHODS TO REPROGRAM MOBILE DEVICES INCLUDING A CROSS-MATRIX CONTROLLER TO PORT CONNECTION
#20DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THREAD PERFORMANCE
#21ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM
#22PROCESSOR FOR CONFIGURABLE PARALLEL COMPUTATIONS
#23Multicore shared cache operation engine
#24Configurable cache for coherent system
#25Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#26ISA extension for high-bandwidth memory
#27Systems and methods to reprogram mobile devices including a cross-matrix controller to port connection
#28Bank to bank data transfer
#29Artificial intelligence chip and data operation method
#30Memory chip having an integrated data mover
#31Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#32Multicore, multibank, fully concurrent coherence controller
#33CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#34Executing functions in response to reading event indices on an event queue by a state machine
#35Graph-based data flow control system
#36DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
#37MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPECULATION AWARE SHARED MEMORY AND INTERCONNECT
#38System and method for selecting an operating mode, such as a boot mode, of a micro-controller unit
#39Configurable cache for multi-endpoint heterogeneous coherent system
#40Data pipeline circuit supporting increased data transfer interface frequency with reduced power consumption, and related methods
#41Delayed snoop for improved multi-process false sharing parallel thread performance
#42Multicore shared cache operation engine
#43Graph-based data flow control system
#44Data processing apparatus having multiple processors and multiple interfaces
#45Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#46Systems and methods to reprogram mobile devices via a cross-matrix controller to port connection
#47Method and system for automatically configuring I/O port
#48Multi-processor bridge with cache allocate awareness
#49COMMUNICATION CONTROL DEVICE AND TRANSCEIVER FOR A USER STATION OF A SERIAL BUS SYSTEM, AND METHOD FOR COMMUNICATING IN A SERIAL BUS SYSTEM
#50MULTICORE SHARED CACHE OPERATION ENGINE
#51Processor for configurable parallel computations
#52Circuit architecture mapping signals to functions for state machine execution
#53ISA extension for high-bandwidth memory
#54Memory chip having an integrated data mover
#55Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#56Bank to bank data transfer
#57Lightweight proxy for handling SCSI commands in an active array-standby array configuration
#58PROCESSING SYSTEM FOR SCHEDULING AND ITS MEMORY ACCESS METHOD
#59Multichip package link
#60System on chip comprising a plurality of master resources
#61Link width scaling across multiple retimer devices
#62Distributed error detection and correction with hamming code handoff
#63Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect
#64Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#65Credit aware central arbitration for multi-endpoint, multi-core system
#66Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#67Multi-power-domain bridge with prefetch and write merging
#68Multicore, multibank, fully concurrent coherence controller
#69Delayed snoop for improved multi-process false sharing parallel thread performance
#70Multicore shared cache operation engine
#71Configurable cache for multi-endpoint heterogeneous coherent system
#72Multi-processor bridge with cache allocate awareness
#73Multicore shared cache operation engine
#74Hardware component detections
#75Master chip, slave chip, and inter-chip DMA transmission system
#76Fast non-volatile storage device recovery techniques
#77Advanced peripheral bus based serial peripheral interface communication device
#78Wake-up control method and device for body control module
#79Selectable peripheral logic in programmable apparatus
#80Selectable peripheral logic in programmable apparatus
#81Selectable peripheral logic in programmable apparatus
#82Link width scaling across multiple retimer devices
#83ISA extension for high-bandwidth memory
#84Dual in-line memory module (DIMM) programmable accelerator card
#85Accelerator architecture on a programmable platform
#86Device for simulating multicore processors
#87Programmable adapter between slow peripherals and network on-chip interfaces
#88Bank to bank data transfer
#89Bank to bank data transfer
#90Method for simulating execution of an application on a multi-core processor
#91Selectable peripheral logic in programmable apparatus
#92Execution windows for an input module of an industrial controller
#93Multichip package link
#94Data bus logger
#95Management processor using code from peripheral device
#96Asynchronous finite state machines
#97Master slave smart contact lens system
#98Method for performing communication between peripheral devices of mobile terminal and mobile terminal
#99SYSTEMS AND METHODS FOR SINGLE-WIRE CONTROL OF A SLAVE INTEGRATED CIRCUIT
#100Circuit having a variable output and a converter controller including same
#101Control apparatus with access monitoring unit configured to request interrupt process
#102Encoding for multi-device synchronization of devices
#103Semiconductor device, method of operating semiconductor device and system incorporating same
#104Non-volatile storage system with compute engine to accelerate big data applications
#105Method and apparatus for coding image information for display
#106Circuit architecture mapping signals to functions for state machine execution
#107Integrated data concentrator for multi-sensor MEMS systems
#108Receiver architecture
#109High performance interconnect link state transitions
#110Multichip package link
#111Integrated circuit having ADC, DSP and computing units
#112Data returned responsive to executing a start subchannel instruction
#113Single relay SDIO interface with multiple SDIO units
#114Swap method and Electronic System thereof
#115Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous
#116Methods and systems for routing in a state machine
#117Multi-mode agent
#118User configurable terminals for an input module of an industrial controller
#119Remapping in a memory device
#120System on chip (SOC) and method for handling interrupts while executing multiple store instructions
#121Reducing required battery capacity for data backup in a storage system with multiple controllers
#122Data processing system for a graphical interface and graphical interface comprising such a data processing system
#123Multicore data processing system with local and global input/output devices and graphical interface comprising such a data processing system
#124Data returned responsive to executing a start subchannel instruction
#125Field calibration system and method
#126Method of verifying layout of mask ROM
#127Method for filtering cached input/output data based on data generation/consumption
#128Extended input/output measurement word facility for obtaining measurement data in an emulated environment
#129Control of semiconductor devices
#130General input/output architecture, protocol and related methods to implement flow control
#131Automatically aligning virtual blocks to physical blocks
#132Techniques for transmitting a command to control a peripheral device through an audio port
#133Method for filtering cached input/output data based on data generation/consumption
#134Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous
#135Event generation in an input module for an industrial controller
#136Integrated counters in an input module for an industrial controller
#137System for monitoring status of modules in an industrial controller
#138Peer communication between modules in an industrial controller
#139Pulse width modulated outputs for an output module in an industrial controller
#140I/O write request handling in a storage system
#141General input/output architecture, protocol and related methods to implement flow control
#142General input/output architecture, protocol and related methods to implement flow control
#143Configuring signals based on device conditions
#144General input/output architecture, protocol and related methods to implement flow control
#145Extended input/output measurement word facility for obtaining measurement data in an emulated environment
#146Implementing drive list mode for reads and writes for hard disk drives
#147Load balancing systems and methods of MAC learning in multi-slot architectures
#148Method and apparatus for transferring data from a first domain to a second domain
#149Reconfigurable control system for controlling a target apparatus, and method for reconfiguration during operation of the control system
#150Remapping and compacting in a memory device
#151General input/output architecture, protocol and related methods to implement flow control
#152General input/output architecture, protocol and related methods to implement flow control
#153General input/output architecture, protocol and related methods to implement flow control
#154Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous
#155Methods and systems for routing in a state machine
#156Data returned responsive to executing a Start Subchannel instruction
#157Image display apparatus and control method
#158Data returned responsive to executing a start subchannel instruction
#159Method and system for receiving commands using a scoreboard on an infiniband host channel adaptor
#160MULTIPLE OVERLAPPING BLOCK TRANSFERS
#161Input module for an industrial controller
#162Output module for an industrial controller
#163Industrial control system with distributed motion planning
#164Extended input/output measurement word facility for obtaining measurement data
#165Apparatus and methods for real-time routing of received commands in a split-path architecture storage controller
#166Audio data processing in a low power mode
#167Image display apparatus and control method
#168Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous
#169Extended input/output measurement word facility and emulation of that facility
#170Data processing apparatus and method for connection to interconnect circuitry
#171Method, apparatus and system for controlling peripheral devices in communication with a playout device using a high definition multimedia interface
#172Integrated Access Cable
#173Input output control apparatus with a plurality of ports and single protocol processing circuit
#174METHOD AND APPARATUS FOR USING MULTIPLE PROTOCOLS ON A COMMUNICATION LINK
#175I/O controller and descriptor transfer method
#176Dynamic state configuration restore
#177SYSTEM AND METHOD FOR UPDATING THE STATUS OF AN ASYNCHRONOUS, IDEMPOTENT MESSAGE CHANNEL
#178Input/Output completion system for a data processing platform
#179Input/output completion system and method for a data processing platform
#180Repeat CCW count argument for device command word processing
#181Media processing method and device
#182Transport control channel program chain linking including determining sequence order
#183Transport control channel program message pairing
#184Swapping PPRC secondaries from a subchannel set other than zero to subchannel set zero using control block field manipulation
#185MULTIPLE OVERLAPPING BLOCK TRANSFERS
#186Data processing system running on a plurality of operating systems (OS) and enabling a channel device to simultaneously perform processing associated with the plurality of operating systems
#187Method of merging and incremental construction of minimal finite state machines
#188Processing of data to suspend operations in an input/output processing log-out system
#189Providing extended measurement data in an I/O processing system
#190Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous
#191Extended measurement word determination at a channel subsystem of an I/O processing system
#192Processing of data to suspend operations in an input/output processing system
#193Programmable Command Sequencer
#194General input/output architecture, protocol and related methods to implement flow control
#195I/O-request processing system and method
#196Method for centralized dynamic link configuration
#197I/O adapter LPAR isolation with assigned memory space
#198Obtaining extended queue measurement data for a range of logical control unit queues
#199Extended input/output measurement word facility, and emulation of that facility
#200Emulation of extended input/output measurement block facilities
#201Method, system, for exchanging data via a buffer pool between a central processing unit and input/output processor that satisfies a predetermined threshold
#202Apparatus for performing I/O sharing & virtualization
#203Synchronized memory channels with unidirectional links
#204Integrated multimedia system
#205Gathering I/O Measurement Data During an I/O Operation Process
#206General input/output architecture, protocol and related methods to manage data integrity
#207Extended input/output measurement block
#208Processor condition sensing circuits, systems and methods
#209Apparatus for high-speed streaming data transmission using PMEM controller and method thereof
#210Processing multiplex sublayer data unit data in hardware
#211Obtaining queue measurement data for a range of logical control unit queues
#212Gathering I/O measurement data during an I/O operation process
#213Data processing system
#214Managing sets of input/output communications subadapters of an input/output subsystem
#215Input output control apparatus with a plurality of ports and single protocol processing circuit
#216Future activity list for peripheral bus host controller
#217Generalized resettable memory