SHARED ROUTING AND SENSING IN A MULTI-TILE DIGITAL IN-MEMORY COMPUTATION (DIMC) NEURAL PROCESSING UNIT (NPU)

INTERNAL COMMUNICATION LINK

CONFIGURABLE BRIDGE FOR MULTI-CHIP PACKAGE

DATA TRANSFER

CONNECTOR AND MOTHERBOARD

SPI INTERFACE SYSTEM, SPI DATA WRITING METHOD, AND SPI DATA READING METHOD

ARM SECURITY FIRMWARE CONFIGURATION METHOD AND APPARATUS APPLIED TO ARM SERVER

MULTIPLE TIERS NETWORK-ON-CHIP ARCHITECTURE

FLASH-DRAM HYBRID MEMORY MODULE

Communication with a Data Storage Device with a Web Application

METHODS AND APPARATUS TO UPDATE FIRMWARE USING BULK REGISTER ACCESS

MULTI-TILE VIRTUAL MACHINES WITH BOUNDARY SWITCH CONFIGURATION

COMMUNICATION DEVICE AND RECEPTION DATA PROCESSING METHOD IN COMMUNICATION DEVICE

BRIDGING FIELD BUS MODULE AND METHOD FOR OPERATING A BRIDGING FIELD BUS MODULE

ATOMIC GROUP PARTITIONING FOR RECONFIGURABLE PROCESSORS

MOBILE DEVICES AND OPERATION METHODS THEREOF, SYSTEMS, AND COMPUTER-READABLE STORAGE MEDIUMS

Bond-to-Bond Die Interface

PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME

BRIDGING AGENT FOR AN EMBEDDED CONTROLLER IN AN ADVANCED REDUCED INSTRUCTION SET COMPUTER MACHINES (ARM) BASED ARCHITECTURE SYSTEM

APPARATUS AND METHODS FOR ESTABLISHING LINK BANDWIDTHS WITHIN DIE INTERCONNECT ARCHITECTURES

PROCESSING SYSTEM AND PROCESSING METHOD FOR NEURAL NETWORK

SYSTEM AND METHOD FOR REQUESTING MEMORY ACCESS

DEVICE, SYSTEM AND METHODS FOR ACCESSING MULTIPLE NVMe NAMESPACES

FIELD-PROGRAMMABLE GATE ARRAY STRUCTURE FOR IMPLEMENTING OUT-OF-BAND BRDIGING, OUT-OF-BAND BRIDGING SYSTEM AND METHOD, AND SERVER

PACKET PROCESSING FOR CLUSTERED CONTAINERS USING INTERNAL BRIDGING AND AN OFFLOAD ARCHITECTURE

GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS

FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEM

BUS BRIDGE, CHIP, AND LiDAR

PARTITIONING FOR RECONFIGURABLE DATA PROCESSORS

Interface Bus Combining

MULTI-DIE SYSTEMS WITH MODULAR DIE-TO-DIE LINK MACROS FOR ENABLING DIE-TO-DIE COMMUNICATION

LATENCY OPTIMIZATION IN PARTIAL WIDTH LINK STATES

DELAYED SNOOP FOR MULTI-CACHE SYSTEMS

FLASH-DRAM HYBRID MEMORY MODULE

SYSTEM AND METHOD FOR MULTI-CORE ACCESS CONTROL ON A DUAL-CORE MICROCONTROLLER

TECHNIQUES FOR PERFORMING DATA OPERATIONS USING A DATA BRIDGE

MULTICORE SHARED CACHE OPERATION ENGINE

CIRCUIT DEVICE WITH MULTIPLE PARALLEL DATA PATHS

CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM

Seamlessly Integrated Microcontroller Chip

MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER

DETECTION SYSTEM SENDING CALCULATED DATA AND RAW DATA

SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME

MEMORY SYSTEM

WEBCAM AND DATA PROCESSING METHOD THEREOF

PERFORMANCE TEST METHOD AND TEST APPARATUS

APPARATUS AND METHOD FOR EFFICIENTLY PACKING DATA FOR TRANSMISSION OVER INTERCONNECT FABRICS

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

QUASI-VOLATILE MEMORY DEVICE WITH A BACK-CHANNEL USAGE

EFFICIENT DEVICE RECOVERY

Cross network bridging

APPARATUS AND MECHANISM FOR PROCESSING NEURAL NETWORK TASKS USING A SINGLE CHIP PACKAGE WITH MULTIPLE IDENTICAL DIES

METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER

VIRTUAL NETWORK PRE-ARBITRATION

INCREASED DATA INTEGRITY FOR AUTHENTICATED ENCRYPTION ALGORITHMS

HIGH BANDWIDTH THREE-DIMENSIONAL SYSTEM-ON-CHIP

MEMORY SYSTEM WITH SELECTIVELY INTERFACEABLE MEMORY SUBSYSTEM

RESILIENT I/O INTERCONNECT

FARMING DATA COLLECTION AND EXCHANGE SYSTEM

COMPUTER SYSTEM AND A COMPUTER DEVICE

RECONFIGURABLE CHANNEL INTERFACES FOR MEMORY DEVICES

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

METHODS AND APPARATUS FOR PROVIDING A BRIDGING DEVICE FOR INTERFACING BETWEEN D-PHY AND C-PHY

RECONFIGURABLE PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) DATA PATH TRANSPORT TO REMOTE COMPUTING ASSETS

PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) DEVICE METHOD FOR DELAYING COMMAND OPERATIONS BASED ON GENERATED THROUGHPUT ANALYSIS INFORMATION

CXL FABRIC EXTENSIONS

ASYNCHRONOUS FIFO READ/WRITE CONTROL METHOD AND SYSTEM, AND ELECTRONIC DEVICE

METHOD AND SYSTEM FOR IN-LINE ECC PROTECTION

ELECTRONIC DEVICE AND OPERATING METHOD OF THE SAME

MEMORY MODULE WITH COMPUTATION CAPABILITY

FLASH MEMORY ARCHITECTURE IMPLEMENTING INTERCONNECTION REDUNDANCY

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO

SCALABLE AND CONFIGURABLE NON-TRANSPARENT BRIDGES

SCALABLE AND CONFIGURABLE NON-TRANSPARENT BRIDGES

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

DATA CONVEYANCE AND COMMUNICATION OF THREE OR MORE LVDC ENABLED DEVICES

PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME

MOBILE DEVICES AND OPERATION METHODS THEREOF, SYSTEMS, AND COMPUTER-READABLE STORAGE MEDIUMS

MULTICORE SHARED CACHE OPERATION ENGINE

STACKED DEVICE SYSTEM

Debug Trace Fabric for Integrated Circuit

APPARATUS AND MECHANISM FOR PROCESSING NEURAL NETWORK TASKS USING A SINGLE CHIP PACKAGE WITH MULTIPLE IDENTICAL DIES

FLASH REGISTRY WITH ON-DISK HASHING

HARD IP BLOCKS WITH PHYSICALLY BIDIRECTIONAL PASSAGEWAYS

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

CONFIGURABLE CACHE FOR COHERENT SYSTEM

Management of endpoint devices utilizing tag bridge devices

WIRELESS INTERFACE SHARING FOR OUT-OF-BAND PROCESSORS IN HETEROGENEOUS COMPUTING PLATFORMS

SYSTEM AND METHOD FOR AGGREGATING SERVER MEMORY

SYSTEM-ON-CHIP AND AN INTERCONNECT BUS INCLUDED IN THE SYSTEM ON CHIP

FLEXIBLE BACKPLANE FOR SYSTEM OPERATIONS

MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING

vRAN with PCIe Fronthaul

INTERFACE FOR MEMORY READOUT FROM A MEMORY COMPONENT IN THE EVENT OF FAULT

IN-SYSTEM VALIDATION OF INTERCONNECTS BY ERROR INJECTION AND MEASUREMENT

SYSTEMS, METHODS, AND APPARATUS TO ENABLE DATA AGGREGATION AND ADAPTATION IN HARDWARE ACCELERATION SUBSYSTEMS

RETIMER PATH CONTROL METHOD, APPARATUS, AND SYSTEM

SYSTEMS AND METHODS OF TESTING MEMORY DEVICES

Bridge device and method for transferring command and data between a host device and a data storage device

AXI-TO-MEMORY IP PROTOCOL BRIDGE

END-TO-END ISOLATION OVER PCIE

CONFIGURABLE FPGA ACCESS CONTROL

TEST EQUIPMENT HUB

Cross network bridging

INTERFACE CIRCUIT AND METHOD

Redundancy scheme for activating circuitry on a base die of a 3D stacked device

GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS

SYSTEM AND METHOD FOR PROVIDING IN-STORAGE ACCELERATION (ISA) IN DATA STORAGE DEVICES

FIREWALLING COMMUNICATION PORTS IN A MULTI-PORT SYSTEM

Systems and methods to manage security protocol and data model (SPDM) secure communication sessions

TECHNIQUES FOR DATA BUS INVERSION WITH IMPROVED LATENCY

Circular buffer for input and output of tensor computations

Method and apparatus for monitoring a PCIe NTB

DYNAMIC CONFIGURATION OF SPUR CANCELLATION

DATA BUS WIDTH CONFIGURABLE INTERCONNECTION CIRCUITRY

SYSTEMS AND METHODS TO FLUSH DATA IN PERSISTENT MEMORY REGION TO NON-VOLATILE MEMORY USING AUXILIARY PROCESSOR

SYSTEM AND METHOD FOR DUAL-PORT COMMUNICATION AND POWER DELIVERY

Multiprocessor system with improved secondary interconnection network

Flash memory architecture implementing interconnection redundancy

BILLBOARD FOR CONTEXT INFORMATION SHARING

Interface Bus Combining

Farming data collection and exchange system

DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILES

Universal Ethernet Solution

Uniform virtual bus for system-to-system connectivity in an autonomous driving vehicle

Flash registry with on-disk hashing

NETWORK DEVICES WITH MULTI-INTERFACE BRIDGE AND COUNT AGGREGATION AND PUBLISHING CIRCUITRY

CIRCUIT DEVICE WITH MULTIPLE PARALLEL DATA PATHS

METHODS AND APPARATUS FOR OFFLOADING ENCRYPTION

MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS

Quasi-volatile memory device with a back-channel usage

Memory disaggregation and reallocation

ON-CHIP INTEGRATED CIRCUIT, DATA PROCESSING DEVICE, AND DATA PROCESSING METHOD

Reconfigurable peripheral component interconnect express (PCIe) data path transport to remote computing assets

Seamlessly Integrated Microcontroller Chip

METHOD FOR RESPONDING TO COMMAND, STORAGE DEVICE AND STORAGE SYSTEM

Sharing communication lines among multiple buses

Bridge control chip and associated signal processing method

NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION

Combining peripheral component interface express partial store commands along cache line boundaries

MANAGING POWER IN DATA CENTERS

ACTIVE BRIDGE FOR CHIPLET AND MODULE INTER-COMMUNICATION

SYSTEMS AND METHODS TO REPROGRAM MOBILE DEVICES INCLUDING A CROSS-MATRIX CONTROLLER TO PORT CONNECTION

DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THREAD PERFORMANCE

APPARATUS FOR INTERPROCESSOR COMMUNICATION, CONTROL DEVICE HAVING THE APPARATUS AND VEHICLE HAVING THE CONTROL DEVICE, METHOD FOR OPERATING THE APPARATUS

SECURED PERIPHERAL DEVICE COMMUNICATION VIA BRIDGE DEVICE IN VIRTUALIZED COMPUTER SYSTEM

Multi-threaded, self-scheduling processor

Bus training with interconnected dice

Bus training with interconnected dice

SERIALIZED BROADCAST COMMAND MESSAGING IN A DISTRIBUTED SYMMETRIC MULTIPROCESSING (SMP) SYSTEM

Adaptive integrated programmable data processing unit

Thread Commencement Using a Work Descriptor Packet in a Self-Scheduling Processor

INTERFACE APPARATUS FOR DRIVING OPEN PLUGGABLE SPECIFICATION

SYSTEM AND METHOD FOR AN ADAPTIVE STORAGE MEDIA INTERFACE

SYSTEM WITH CACHE-COHERENT MEMORY AND SERVER-LINKING SWITCH

Systems and methods to transport memory mapped traffic amongst integrated circuit devices

Information processing apparatus, information processing system, connection control method, and non-transitory computer readable medium storing connection control program

Stacked device system

Dynamic hardware resource shadowing and memory error protection

Universal serial bus (USB) hub with host bridge function and control method thereof

INTER-DIE COMMUNICATION OF PROGRAMMABLE LOGIC DEVICES

Methods and systems for requesting atomic operations in a computing system

Multi-protocol support on common physical layer

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

System-on-chip and an interconnect bus included in the system on chip

Disaggregation of system-on-chip (SOC) architecture

Computer system and a computer device

Patterned memory-network data transfer

Disaggregation of system-on-chip (SOC) architecture

GRAPHICS PROCESSING INTEGRATED CIRCUIT PACKAGE

Hypervisor bridging of different versions of an IO protocol

Interface for memory readout from a memory component in the event of fault

BUS PROTOCOL FOR MULTIPLE CHIPSETS

Multicore shared cache operation engine

Memory System Topologies Including A Memory Die Stack

Data conveyance and communication of three or more LVDC enabled devices

Method and system for in-line ECC protection

Storage device adjusting data rate and storage system including the same

PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME

Configurable cache for coherent system

Dynamic configuration of input/output controller access lanes

MODULAR QUANTUM SYSTEM WITH DISCRETE LEVELS OF CONNECTIVITY

ORCHESTRATING ALLOCATION OF SHARED RESOURCES IN A DATACENTER

Intelligent path selection and load balancing

Cross network bridging

Flexible on-die fabric interface

Multiple Independent On-chip Interconnect

Semi-programmable and reconfigurable co-accelerator for a deep neural network with normalization or non-linearity

Methods and systems for devices with self-selecting bus decoder

Farming data collection and exchange system

Baseboard management controller module

Server system and method for detecting correctness of connections therein

Transaction generator for on-chip interconnect fabric

Access Optimization in Aggregated and Virtualized Solid State Drives

Cascade communications between FPGA tiles

Virtual network pre-arbitration for deadlock avoidance and enhanced performance

Networking module for instrumentation and control devices

ACTIVE BRIDGE CHIPLET WITH INTEGRATED CACHE

INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR DEVICE

CAPTURE OF EMMC CARD IDENTIFICATION FOR COMPONENT TRACEABILITY OF PCIE DAUGHTER CARD

Signal bridging using an unpopulated processor interconnect

Methods and systems for pattern recognition processing

Efficient and low power reference voltage mixing

Multi-die integrated circuit with data processing engine array

Top level network and array level network for reconfigurable data processors

VERTICAL AND HORIZONTAL BROADCAST OF SHARED OPERANDS

Memory disaggregation and reallocation

External exchange connectivity

Efficient storage of error correcting code information

Interconnected memory grid with bypassable units

Electronic device and method for fabricating the same

COMMUNICATION SYSTEM AND METHOD

USB connector functionality modification system

Data flow monitoring in a multiple core system

VRAN with PCIe fronthaul

Systems, methods, and apparatus to enable data aggregation and adaptation in hardware acceleration subsystems

OPTICAL BRIDGE INTERCONNECT UNIT FOR ADJACENT PROCESSORS

Chiplet system and positioning method thereof

Daisy-chain SPI integrated circuit and operation method thereof

Multi-partitioned global data system

UNIVERSAL SERIAL BUS (USB) CABLE WITH INTEGRATED SWITCH FOR CHANGING FUNCTIONAL MODES

Seamlessly integrated microcontroller chip

Dynamic hardware resource shadowing and memory error protection

SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME

DETECTION SYSTEM SENDING CALCULATED DATA AND RAW DATA

Bridge device and data storage system

USB integrated circuit, operation method of USB integrated circuit and USB device

Method and apparatus for providing a bridging device for interfacing between D-PHY and C-PHY

SMART SCALABLE DESIGN FOR A CROSSBAR

Protocol aware bridge circuit for low latency communication among integrated circuits

DATA TRANSMISSION METHOD AND DATA TRANSMISSION SYSTEM

Reconfigurable peripheral component interconnect express (PCIe) data path transport to remote computing assets

Rack controller with native support for intelligent patching equipment installed in multiple racks

Data encoding using spare channels in a memory system

NON-VOLATILE MEMORY STORAGE AND INTERFACE

Electronic system and related method for providing multiple hosts with network connectivity and remote wake-up

High-availability (HA) management networks for high performance computing platforms

Routing assignments based on error correction capabilities

Methods and apparatus for offloading encryption

Electronic device and operation method of sleep mode thereof

Interconnect system

Apparatus and method for role-based register protection for TDX-IO

Interconnect interface

Data conveyance and communication scheme for two party low voltage drive circuit communication

Intra-chip and inter-chip data protection

Reconfigurable server and server rack with same

Systems and methods to reprogram mobile devices including a cross-matrix controller to port connection

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

Dynamic configuration of spur cancellation

Application-transparent near-memory processing architecture with memory channel network

Low latency host processor to coherent device interaction

Graphics processor and information processing system

On-demand packetization for a chip-to-chip interface

PHYSICALLY DISTRIBUTED CONTROL PLANE FIREWALLS WITH UNIFIED SOFTWARE VIEW

Loop execution in a reconfigurable compute fabric

Systems and methods to flush data in persistent memory region to non-volatile memory using auxiliary processor

Broadcast scope selection in a data processing system utilizing a memory topology data structure

QUEUE BYPASSING INTERRUPT HANDLING

Data network having at least three line branches, which are connected to one another via common star node as well as a motor vehicle and operating method for the data network

Integrated circuit device with multiple direct memory access (DMA) data paths

Transporting request types with different latencies

Systems and methods of testing memory devices

INTER-CHIPLET ROUTING OF TRANSACTIONS ACROSS MULTI-HETEROGENEOUS CHIPLETS USING HIERARCHICAL ADDRESSING

Graphics processing integrated circuit package

DISAGGREGATED MEMORY SERVER

System and method for providing in-storage acceleration (ISA) in data storage devices

Flash memory architecture implementing interconnection redundancy

Virtual developmental environment apparatus, method, and recording medium

DATA TRANSMISSION METHOD AND APPARATUS, AND RELATED ASSEMBLY

LIN communication circuit and a method of communicating between LIN busses

DYNAMICALLY SCALABLE AND PARTITIONED COPY ENGINE

PCIE-BASED COMMUNICATIONS METHOD AND APPARATUS

Interface bus combining

Routing and converting traffic based on communication protocols

Communication system, superior control device and subordinate control device

Bus system and method for operating a bus system

Ordered data sub-component extraction

MAC processing pipelines, circuitry to control and configure same, and methods of operating same

Selecting, from a pool of items, a selected item to be associated with a given request

Peripheral component interconnect express device and operating method thereof

System with cache-coherent memory and server-linking switch

Billboard for context information sharing

Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure

Multicore, multibank, fully concurrent coherence controller

CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM

Debug trace fabric for integrated circuit

Networking module for instrumentation and control devices

Method and apparatus for providing C-PHY interface via FPGA IO interface

Transaction generator for on-chip interconnect fabric

On-chip integrated circuit, data processing device, and data processing method

CCIX port management for PCI express traffic

Ordered delivery of data packets based on type of path information in each packet

Flexible high-availability computing with parallel configurable fabrics

Additional communication in standardized pinout of a bidirectional interface between a first and second communication device

Apparatus and method for fault handling of an offload transaction

Localized NoC switching interconnect for high bandwidth interfaces

Memory system topologies including a memory die stack

System including PIPE5 to PIPE4 converter and method thereof

Method and device for operating a transfer device

Multiple independent on-chip interconnect