Processors, methods, and systems with a configurable spatial accelerator

RING NETWORK SYSTEM USING PERIPHERAL COMPONENT INTERCONNECT EXPRESS AND SETTING METHOD THEREOF

Adjustment of buffer credits and other parameters in a startup phase of communications between a plurality of channels and a control unit

MODULAR COMMAND DEVICE FOR ELECTROVALVE ISLANDS

Implementing device models for virtual machines with reconfigurable hardware

Server system

Method, device, and system for buffering data for read/write commands in NVME over fabric architecture

Data processing device, data processing system and method

EFFICIENT DATA MOVEMENT WITHIN FILE SYSTEM VOLUMES

Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field

Bus device with programmable address

System for exchanging information between wireless peripherals and back-end systems via a peripheral hub

Method and apparatus for handling outstanding interconnect transactions

Methods and apparatus for providing peripheral sub-system stability

Methods and apparatus for providing access to peripheral sub-system registers

BOARD MANAGEMENT CONTROLLER PERIPHERAL CARD, HOST SYSTEM WITH THE SAME, AND METHOD FOR MANAGING HOST PERIPHERAL MEMBER BY THE SAME

Thunderbolt Flash Drive

Computer subsystem and computer system with composite nodes in an interconnection structure

Computing system with a nonvolatile storage and operating method thereof

Ascertaining configuration of a virtual adapter in a computing environment

Ascertaining configuration of a virtual adapter in a computing environment

High performance interconnect physical layer

Universal serial bus emulation layer

Reconfigurable fabric direct memory access with multiple read or write elements

RECONFIGURABLE FABRIC ACCESSING EXTERNAL MEMORY

Platform communication protocol

Firm channel paths

Implementing sideband control structure for PCIE cable cards and IO expansion enclosures

Implementing sideband control structure for PCIE cable cards and IO expansion enclosures

Selective purging of PCI I/O address translation buffer

Processor core to coprocessor interface with FIFO semantics

Systems, devices, and methods for selective communication through an electrical connector

Early identification in transactional buffered memory

Preventing input/output (I/O) traffic overloading of an interconnect channel in a distributed data storage system

Information processing apparatus, information processing method, and program

Switching device, peripheral component interconnect express system, and method for initializing peripheral component interconnect express system

Optimized credit return mechanism for packet sends

APPARATUS AND METHOD FOR IDENTIFYING AND MANAGING INPUT/OUTPUT (I/O) CHANNEL SPARES FOR CONTROL AND INSTRUMENTATION SYSTEMS IN INDUSTRIAL PLANTS

CONTROL CIRCUIT BOARD, MICRO-SERVER, CONTROL SYSTEM AND CONTROL METHOD THEREOF

Information processing apparatus

High performance interconnect link layer

Network-accessible data volume modification

POINT-TO-POINT CHECKOUT AUTOMATION

Physical Layer for Peripheral Interconnect with Reduced Power and Area

Dragonfly processor interconnect network

System transparent retimer

Systems and methods for deserializing data

Modifications to a stream processing topology during processing of a data stream

Semiconductor device and data processing system selectively operating as one of a big endian or little endian system

Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines

Data bus driving circuit, and semiconductor device and semiconductor memory device including the same

Semaphore for multi-core processor

Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system

Accessing data in accordance with an execution deadline

Control messaging in multislot link layer flit

Message translator

Storage system, method, and apparatus for processing multi-layer protocol encapsulation or decapsulation operation requests

NoC interconnect with linearly-tunable QoS guarantees for real-time isolation

PIN-CONFIGURABLE INTERNAL BUS TERMINATION SYSTEM

Generic physical location codes for virtual system and partition cloning

Barcode reader and accessory for the barcode reader

Power handling in a scalable storage system

Power Efficient Distributed Beam Forming Architecture Using Interconnected Processing Nodes

Semiconductor device

Flattening portal bridge

Method and apparatus for controlling access to a common bus by multiple components

Optimized credit return mechanism for packet sends

Non-uniform memory access support in a virtual environment

METHOD FOR OPERATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM

Signal path verification device

HOST CONTROLLER AND PROGRAM EXECUTED BY HOST CONTROLLER

Switching of host network traffic through baseboard management controller (BMC)

Dynamic Re-Allocation of Computer Bus Lanes

Non-transitory computer-readable recording medium having stored therein a communication algorithm determination program, communication algorithm determination method, and information processing device executing a communication algorithm determination program

Configurable IO-channel system with embedded microcontroller

Systems and methods of in-situ digital eye characterization for serial data transmitter circuitry

System for distributed computing and storage

Techniques for inter-component communication based on a state of a chip select pin

High performance interconnect link layer

High performance interconnect physical layer

High performance interconnect

High performance interconnect physical layer

Synchronous input/output replication of data in a persistent storage control unit

Synchronous input/output replication of data in a persistent storage control unit

Scrambling bit transmissions

Sorting system

High performance interconnect physical layer

System and method for providing personality switching in a solid state drive device

Debug support for block-based processor

Instruction block address register

Prefetching instruction blocks

Broadcast channel architectures for block-based processors

Block-based processor including topology and control registers to indicate resource sharing and size of logical processor

Multi-nullification

Write nullification

Store nullification in the target field

Implicit program order

Register read/write ordering

Dynamic generation of null instructions

Generation and use of memory access instruction order encodings

Multimodal targets in a block-based processor

Dense read encoding for dataflow ISA

Distinct system registers for logical processors

Block-based processor core composition register

Initiating instruction block execution using a register access instruction

Data bus inversion (DBI) encoding based on the speed of operation

Efficient encoding and decoding architecture for high-rate data transfer through a parallel bus

Transaction expansion for NoC simulation and NoC design

Message passing framework for audio/video streaming in a topology of devices

Semiconductor device and data processing system selectively operating as one of a big endian or little endian system

Data processing device, data processing system and method

Communications control system with a serial communications interface and a parallel communications interface

Hardware data structure for tracking ordered transactions

Method and system for flexible credit exchange within high performance fabrics

Backboard for hard disk drive and electronic device using the backboard

Inter-component communication including posted and non-posted transactions

Delivering interrupts through non-transparent bridges in a PCI-express network

Multi-processor startup system

Method and apparatus for accessing multiple storage devices from multiple hosts without use of remote direct memory access (RDMA)

Management of allocation for alias devices

Data processing system and data processing method

System transparent retimer

MultiGig solution on conventional SGMII and XFI capable system

Firmware updating method

Multi-processor startup system

ADD-ON DEVICE AND SERVER USING THE SAME

PCI express to PCI express based low latency interconnect scheme for clustering systems

Management of allocation for alias devices

System and method of interfacing co-processors and input/output devices via a main memory system

Systems and methods for enabling virtual keyboard-video-mouse for external graphics controllers

NVM express controller for remote access of memory and I/O over Ethernet-type networks

Semiconductor device

Multi-function, modular system for network security, secure communication, and malware protection

Adjustment of buffer credits and other parameters in a startup phase of communications between a plurality of channels and a control unit

Method and system for bidirectional communication

Computer subsystem and computer system with composite nodes in an interconnection structure

Apparatus and method for virtualizing network interface

Disjoint array computer

Photonics-Optimized Processor System

Allocating virtual resources to root PCI bus

Delay compensation

System for exchanging information between wireless peripherals and back-end systems via a peripheral hub

CONTROLLER AREA NETWORK BUS

Adapter board system

WIRELESS MODULE

Minimizing thermal impacts of local-access PCI devices

Computer, server, module, connector set, assembly method, control method, and opening control program

APPARATUS AND METHOD FOR PROCESSING SIGNAL

Methods and Apparatus for Efficient Network Analytics and Computing Card

Methods and Apparatus for IO, Processing and Memory Bandwidth Optimization for Analytics Systems

Reading data from storage via a PCI express fabric having a fully-connected mesh topology

Writing data to storage via a PCI express fabric having a fully-connected mesh topology

Selective purging of PCI I/O address translation buffer

Microprocessor systems

Information processing apparatus

Configurable multi-lane scrambler for flexible protocol support

Coupling parallel event-driven computation with serial computation

COUPLING PARALLEL EVENT-DRIVEN COMPUTATION WITH SERIAL COMPUTATION

Input/output device for an electronic cabinet and cabinet comprising such a device

Systems and methods for power optimization at input/output nodes of an information handling system

Preventing input/output (I/O) traffic overloading of an interconnect channel in a distributed data storage system

Circuits and methods for inter-processor communication

Methods and systems for filtering collected QOS data for predicting an expected range for future QOS data

Multi-function ports on a computing device

Ascertaining configuration of a virtual adapter in a computing environment

Ascertaining configuration of a virtual adapter in a computing environment

Communication apparatus, portable terminal apparatus, and communication system

Determination of a device function asserting a detected spurious interrupt

Multi-mode system on a chip

Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing

Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric

Semiconductor device and data processing system selectively operating as one of a big endian or little endian system

Tag allocation for non-posted commands in a PCIe application layer

Methods and apparatus for controlled recovery of error information between independently operable processors

Input/output control device, input/output control system, and input/output control method for conversion of logical address of instruction into local address of device specified in instruction

Virtual PCI expander device

Electronic system and method of switching operating systems thereof

System and method for a low emission network

Power adapter with switchable output voltage control

Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions

Dynamically assigning lanes over which signals are transmitted to mitigate electromagnetic interference (EMI)

High performance interconnect

SYMMETRICALLY COUPLED DIFFERENTIAL CHANNEL

Method, apparatus and system for integrating devices in a root complex

Pin-configurable internal bus termination system

Peripheral component interface (PCI) system and method for expanding PCI nodes in an information handling system

DEVICE TABLE IN SYSTEM MEMORY

Early identification in transactional buffered memory

Automatic failover and failback between primary and secondary storage systems

Enhanced Data Bus Invert Encoding for OR Chained Buses

Data transmission using PCIe protocol via USB port

Power delivery and data transmission using PCIe protocol via USB type-C port

Implementing dynamic SRIOV virtual function resizing

Computer Readable Storage Media and Updating Method Thereof

Processing input/output requests using proxy and owner storage systems

Subscriber station for a bus system and method for improving the error tolerance of a subscriber station of a bus system

Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines

Method of connecting a PCIe bus extension system

Server on a chip and node cards comprising one or more of same

Implementing and processing extent granularity authorization mechanism in CAPI adapters

Implementing and processing extent granularity authorization mechanism in CAPI adapters

COMMUNICATION CONTROL DEVICE, METHOD OF COMMUNICATING A FRAME, AND STORAGE MEDIUM

Bridge for bus-powered peripheral device power management

Method and system for a flexible interconnect media in a point-to-point topography

Field bus coupler for connecting input/output modules to a field bus, and method of operation for a field bus coupler

Arbitration in an SRIOV environment

Arbitration in an SRIOV environment

Peripheral component interconnect express controllers configured with non-volatile memory express interfaces

Barcode reader and accessory for the barcode reader

BARCODE READER AND ACCESSORY FOR THE BARCODE READER

Memory mapping method and memory mapping system

Programmable validation of transaction requests

Network traffic processing

Network traffic processing

INTEGRATED ADAPTER FOR THIN COMPUTING DEVICES

ADAPTER CARD FOR THIN COMPUTING DEVICES

PCI express fabric routing for a fully-connected mesh topology

Information processing apparatus, communication method and information processing system for communication of global data shared by information processing apparatuses

Physical layer network interface module (PHY-NIM) adaptation system

Increased bandwidth of ordered stores in a non-uniform memory subsystem

Increased bandwidth of ordered stores in a non-uniform memory subsystem

Two modes of a configuration interface of a network ASIC

Information processing apparatus, information processing method, and recording medium

Peripheral protocol negotiation

Industrial Server System

ELECTRONIC DEVICE AND SYSTEM FOR SHARING THE EDID OF A DISPLAY AMONG MULTIPLE HOSTS

System and method to provide file system functionality over a PCIe interface

Shared virtualized local storage

Priority arbitration for interference mitigation

Multi-channel, selectable identity tagging data translator and method

Reconfigurable Modular Computing Device

Probabilistic flit error checking

System and method for controlling various aspects of PCIe direct attached nonvolatile memory storage subsystems

Variable frame length virtual GPIO with a modified UART interface

Portable device with data transmission between main system and subsystem and control method therefor

Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media

Efficient data movement within file system volumes

STORAGE SYSTEM AND TEST METHOD FOR TESTING PCI EXPRESS INTERFACE

Reset of single root PCI manager and physical functions within a fabric

Delay circuits and related systems and methods

Debug data saving in host memory on PCIE solid state drive

Environmental monitor device

Hardware data structure for tracking ordered transactions

Sharing unclaimed USB devices as PCI devices

CONNECTOR WITH IN-CIRCUIT PROGRAMMING

Universal serial bus emulation layer

System and method for providing personality switching in a solid state drive device

Methods and apparatus to effect hot reset for an on die non-root port integrated device

Environmental Sensing System

Environmental Sensor Device

Dynamic vehicle bus subscription

High-speed serial ring

Return available PPI credits command

Using a credits available value in determining whether to issue a PPI allocation request to a packet engine

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

System interconnect dynamic scaling handshake using spare bit-lane

System interconnect dynamic scaling handshake using spare bit-lane

Configurable memory circuit system and method

Storage system, method, and apparatus for processing multi-layer protocol encapsulation or decapsulation operation requests

SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM

MEMORY STORAGE WITH BATTERY AND SOLAR CELLS

PCI EXPRESS CLUSTER

Physical layer for peripheral interconnect with reduced power and area

Method and system for communication of device information

Storage control devices and invoking method thereof

Mode selective balanced encoded interconnect

Systems, devices, and methods for selective communication through an electrical connector

Adaptive circuit board assembly and flexible PCI express bus

SYSTEM AND METHOD FOR BUS WIDTH CONVERSION IN A SYSTEM ON A CHIP

Universal serializer architecture

Time multiplexing at different rates to access different memory types

Methods and systems for multiple bus generator and load control

AUTOMATICALLY ADJUSTABLE, CHARGE-ONLY, USB ADAPTER

Interconnection network topology for large scale high performance computing (HPC) systems

Input/output acceleration in virtualized information handling systems

Interconnection network topology for large scale high performance computing (HPC) systems

Connection interface switching device for multiple portable devices

Island-based network flow processor with efficient search key processing

Efficient search key controller with standard bus interface, external memory interface, and interlaken lookaside interface

USB transceiver

MEMORY SYSTEM AND DATA STORAGE DEVICE

System for migrating stash transactions

Caching systems and methods for execution within an NVDRAM environment

INPUT SYSTEM

Dynamically configurable analog frontend circuitry

Optimized credit return mechanism for packet sends

Cache load balancing in storage controllers

High throughput register file memory with pipeline of combinational logic

Server system for synchronizing memory data of motherboards

Signal transmission circuit and printed circuit board

USB CONTROLLERS COUPLED TO USB PORTS

Bidirectional data transmission system

SYSTEM AND METHOD FOR COMMUNICATION PORT BASED ASSET MANAGEMENT

Computer processor employing split crossbar circuit for operand routing and slot-based organization of functional units

Universal serial bus (USB) communication systems and methods

Method and apparatus for dynamic node healing in a multi-node environment

Integrated circuit (IC) with reconfigurable digital voltage regulator fabric

Data transfer device and data transfer method

Hybrid repeater for supporting backward compatibility

Link layer to physical layer (PHY) serial interface