190402 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Information transfer, e.g. on bus; Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol
Z-Dimension Cache Layer Pipelining
#2High capacity, high performance memory system
#3BUS CONFIGURATION SYSTEM AND METHOD THEREOF
#4CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
#5Dynamic variation of bus parameters
#6Continuous adaptive data capture optimization for interface circuits
#7High speed interface for multi image sensor device
#8High capacity, high performance memory system
#9MEMORY SYSTEM AND DATA TRANSMISSION METHOD
#10Continuous adaptive data capture optimization for interface circuits
#11Trigger/array for using multiple cameras for a cinematic effect
#12High capacity, high performance memory system
#13Systems and methods for detecting and configuring lanes in a circuit system
#14Memory system and data transmission method
#15Continuous adaptive data capture optimization for interface circuits
#16Trigger/array for using multiple cameras for a cinematic effect
#17Daisy chain streaming mode
#18Daisy chain mode entry sequence
#19Daisy chain complex commands
#20Bus-compatible sensor element and communication system
#21Dual-edge triggered ring buffer and communication system
#22Self-configuring peripheral module
#23Expansion module system
#24Daisy chain control network with data generators and token-forwarding connections
#25Serial communication protocol
#26Memory system and data transmission method
#27Method and system for enumerating digital circuits in a system-on-a-chip (SOC)
#28Method and system for enumerating digital circuits in a system-on-a-chip (SOC)
#29CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
#30Expansion module system
#31Clock tree structure in a memory system
#32Memory system and data transmission method
#33Data processing apparatus with snoop request address alignment and snoop response time alignment
#34Information processing apparatus
#35CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
#36High capacity, high performance memory system
#37Semiconductor device, electronic component, and electronic device
#38Apparatus and method for optimized n-write/1-read port memory design
#39Arbiter verification
#40Method and system for enumerating digital circuits in a system-on-a-chip (SOC)
#41Method and system for enumerating digital circuits in a system-on-a-chip (SOC)
#42Continuous adaptive data capture optimization for interface circuits
#43Transfer for control data over half-duplex link
#44Expansion module system
#45Method and apparatus to enable multiple masters to operate in a single master bus architecture
#46Apparatus for a reduced current wake-up circuit for a battery management system
#47Method of using a field-effect transistor as a current sensing device
#48Storage device, memory card, and communicating method of storage device
#49System method for connecting USB Type-C devices by measuring predetermined test patterns between a plurality of connected accessories
#50ARBITRATING BUS TRANSACTIONS ON A COMMUNICATIONS BUS BASED ON BUS DEVICE HEALTH INFORMATION AND RELATED POWER MANAGEMENT
#51Method for executing, within a multitasking onboard system, an application timed according to a plurality of different time domains including interruption management
#52Communications assembly having logic multichannel communication via a physical transmission path for serial interchip data transmission
#53Method for operating a slave node of a digital bus system
#54Device and method for writing/reading a memory register shared by a plurality of peripherals
#55Power switching in a two-wire conductor system
#56Two-wire communication protocol engine
#57Point-to-point serial peripheral interface for data communication between devices configured in a daisy-chain
#58Memory system and data transmission method
#59Disabling outbound drivers for a last memory buffer on a memory channel
#60Synchronization, re-synchronization, addressing, and serialized signal processing for daisy-chained communication devices
#61Communications architecture for providing data communication, synchronization and fault detection between isolated modules
#62Disabling outbound drivers for a last memory buffer on a memory channel
#63Arbitrating bus transactions on a communications bus based on bus device health information and related power management
#64Information processing apparatus, information processing method, and storage medium
#65High-speed interface for daisy-chained devices
#66Slave device, system including master device and slave device, method for operating the same, and chip package
#67Isolated communication bus and related protocol
#68Memory chain
#69Cascade-able serial bus device with clock and management and cascade methods using the same
#70Disabling outbound drivers for a last memory buffer on a memory channel
#71System and method of sending and receiving data and commands using the TCK and TMS of IEEE 1149.1
#7212C/SMBus ladders and ladder enabled ICs
#73MOTOR DRIVING DEVICE, INTEGRATED CIRCUIT DEVICE, MOTOR DEVICE, AND MOTOR DRIVING SYSTEM
#74Memory channel with bit lane fail-over
#75Cooperation circuit
#76ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM
#77DATA TRANSFER SYSTEM AND DATA TRANSFER METHOD
#78Memory system and data transmission method
#79Memory systems including memory devices coupled together in a daisy-chained arrangement
#80Addressing multi-core advanced memory buffers
#81Method for bus testing and addressing in mass memory components
#82ARCHITECTURE FOR VERY LARGE CAPACITY SOLID STATE MEMORY SYSTEMS
#83Memory channel with bit lane fail-over
#84System having one or more memory devices
#85Memory buffer for an FB-DIMM
#86System, method and storage medium for a multi-mode memory buffer device
#87Data transmission/reception system
#88Flash Memory Control Interface
#89Memory system and method for operating a memory system
#90Scalable memory system
#91METHOD AND SYSTEM FOR A PENDANT BUS PROTOCOL
#92Self timed memory chip having an apportionable data bus
#93Memory controller for daisy chained memory chips
#94Computer system having daisy chained memory chips
#95Method and system for terminating write commands in a hub-based memory system
#96Data transfer method and data transfer device
#97Systems and methods for data transfer
#98Input/output agent having multiple secondary ports
#99Memory channel with unidirectional links
#100Daisy chain cascading devices
#101Reconfigurable communications infrastructure for ASIC networks
#102Memory module and memory device and method of operating a memory device
#103Daisy chain cascading devices
#104Systems and methods for writing data with a FIFO interface
#105Memory system and data transmission method
#106System and method to increase DRAM parallelism
#107Method and system for capturing and bypassing memory transactions in a hub-based memory system
#108System, method and storage medium for a multi-mode memory buffer device
#109SYSTEM AND METHOD FOR DYNAMICALLY ALLOCATING ADDRESSES TO DEVICES COUPLED TO AN INTEGRATED CIRCUIT BUS
#110Data transfer method and data transfer device
#111Method and system for terminating write commands in a hub-based memory system
#112Systems and methods for interconnection of multiple FPGA devices
#113Serial digital communication system and method
#114Method and apparatus for maintaining data density for derived clocking
#115Lane testing with variable mapping
#116Method and system for capturing and bypassing memory transactions in a hub-based memory system
#117Serial peripheral interface system with slave expander
#118Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuit