190442 ⎘
Digital computers in general ; Data processing equipment in general; Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs; Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake; Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
Managing Traffic for Endpoints in Data Center Environments to Provide Cloud Management Connectivity
#2COLLECTIVE COMMUNICATION METHOD AND SYSTEM, AND COMPUTER DEVICE
#3Avoiding use of a subarray of configurable units having a defect
#4Load balancing system for the execution of applications on reconfigurable processors
#5IN-NETWORK COLLECTIVE OPERATIONS
#6Neural processing accelerator
#7Managing traffic for endpoints in data center environments to provide cloud management connectivity
#8Memory network processor
#9Switch for routing data in an array of functional configurable units
#10Defect avoidance in a multidimensional array of functional configurable units
#11Neural processing accelerator
#12Interconnected Dies, Interconnected Microcomponents, Interconnected Microsystems and Their Communication Methods
#13Memory network processor
#14High performance interconnect
#15Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric
#16Component building blocks and optimized compositions thereof in disaggregated datacenters
#17Cache coherent node controller for scale-up shared memory systems having interconnect switch between a group of CPUS and FPGA node controller
#18Neural processing accelerator
#19Memory network processor
#20Node controller direct socket group memory access
#21Internet-of-things (IoT) extended peripheral support for terminals
#22Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric
#23High performance interconnect
#24Dimension shuffling using matrix processors
#25CPU INTERCONNECT APPARATUS AND SYSTEM, AND CPU INTERCONNECT CONTROL METHOD AND CONTROL APPARATUS
#26Switchable topology processor tile and computing machine
#27CPU and multi-CPU system management method
#28System and method for defining machine-to-machine communicating devices and defining and distributing computational tasks among same
#29Switch unit, ethernet network, and method for activating components in an ethernet network
#30Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric
#31Multiprocessor fabric having configurable communication that is selectively disabled for secure processing
#32Storage management for a cluster of integrated computing systems comprising integrated resource infrastructure using storage resource agents and synchronized inter-system storage priority map
#33Policy application server for mobile data networks
#34Network topology for a scalable multiprocessor system
#35Unified network architecture for scalable super-calculus systems
#36Control chip for communicating with wired connection interface by using one configurable pin selectively serving as input pin or output pin
#37Automatically routing super-compute interconnects
#38Automatically routing super-compute interconnects
#39Tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms
#40Method and system for disabling communication paths in a multiprocessor fabric by setting register values to disable the communication paths specified by a configuration
#41Network node and method for controlling resources in a communication network
#42Petaflops router
#43Apparatus and method for routing data among multiple cores
#44Distribution server, data distribution method, and program
#45Hierarchical passive networks
#46Stream processing in optically linked super node clusters of processors by mapping stream graph to nodes and links
#47On-chip and chip-to-chip routing using a processor element/router combination
#48DATA PROCESSING DEVICE AND METHOD
#49Stream processing in super node clusters of processors assigned with stream computation graph kernels and coupled by stream traffic optical links
#50Dynamic network link selection for transmitting a message between compute nodes of a parallel computer
#51Policy application server for mobile data networks
#52Data processing device and method
#53Data processing device and method
#54Network topology for a scalable multiprocessor system
#55Multiprocessor node controller circuit and method
#56Data processing device and method
#57Network topology for a scalable multiprocessor system
#58Effector machine computation
#59Configuring a physical platform in a reconfigurable data center
#60Multiprocessor node controller circuit and method
#61Defect repair circuits for a reconfigurable data processor
#62Flow control in a parallel processing environment
#63Relocate targets to different domains in an emulator