190448 ⎘
Digital computers in general ; Data processing equipment in general; Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs; Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake; Indirect interconnection networks non hierarchical topologies Two dimensional, e.g. mesh, torus
INTERCONNECTED MESH SYSTEMS AND METHODS OF USING SAME
#2Method and system for converting a single-threaded software program into an application-specific supercomputer
#3DISTRIBUTED PROCESSING APPARATUS AND OPERATING METHOD THEREOF
#4DIAGONAL TORUS NETWORK
#5INTERCONNECT ARCHITECTURE ENABLING PATH DIVERSITY FOR STRONGLY ORDERED MESSAGES
#6MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK
#7MULTI-CAST SNOOP VECTORS WITHIN A MESH TOPOLOGY
#8NEURAL NETWORK ACCELERATOR
#9Multiprocessor system with improved secondary interconnection network
#10CONFIGURABLE MEMORY POOL SYSTEM
#11PROCESSOR
#12System-on-chip management controller
#13Multiple Independent On-chip Interconnect
#14EXECUTION ENGINE FOR EXECUTING SINGLE ASSIGNMENT PROGRAMS WITH AFFINE DEPENDENCIES
#15Method and system for converting a single-threaded software program into an application-specific supercomputer
#16DIAGONAL TORUS NETWORK
#17Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration
#18Array processor having an instruction sequencer including a program state controller and loop controllers
#19Multiple independent on-chip interconnect
#20Method and system for converting a single-threaded software program into an application-specific supercomputer
#21Execution engine for executing single assignment programs with affine dependencies
#22Memory-fabric-based processor context switching system
#23Multiprocessor system with improved secondary interconnection network
#24OPTIMIZED FUNCTION ASSIGNMENT IN A MULTI-CORE PROCESSOR
#25Digital processing connectivity
#26Method and system for converting a single-threaded software program into an application-specific supercomputer
#27Information processing apparatus, information processing method and non-transitory computer-readable storage medium for storing information processing program of determining relations among nodes in N-dimensional torus structure
#28Management of access restriction within a system on chip
#29Parallel processing of reduction and broadcast operations on large datasets of non-scalar data
#30Cache partitioning in a multicore processor
#31Execution engine for executing single assignment programs with affine dependencies
#32System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuit
#33Compute-communicate continuum technology
#34Multiprocessor system with improved secondary interconnection network
#35Node controller direct socket group memory access
#36Method and system for converting a single-threaded software program into an application-specific supercomputer
#37Processing apparatus and methods
#38Opcode counting for performance measurement
#39Method and apparatus to build a monolithic mesh interconnect with structurally heterogenous tiles
#40Memory network methods, apparatus, and systems
#41Switchable topology processor tile and computing machine
#42Optimized function assignment in a multi-core processor
#43Power saving for a computer system and computer based on differences between chip regions in processing and communication times
#44Execution engine for executing single assignment programs with affine dependencies
#45Methods, network node and wireless device for handling device capabilities
#46Network topology system and method
#47Cache partitioning in a multicore processor
#48Multiprocessor system with improved secondary interconnection network
#49Scheduling application instances to processor cores over consecutive allocation periods based on application requirements
#50Opcode counting for performance measurement
#51Method and system for converting a single-threaded software program into an application-specific supercomputer
#52Embedding global barrier and collective in a torus network
#53Multiprocessor system with improved secondary interconnection network
#54Direct network having plural distributed connections to each resource
#55Multi-petascale highly efficient parallel supercomputer
#56Execution engine for executing single assignment programs with affine dependencies
#57Opcode counting for performance measurement
#58Cache partitioning in a multicore processor
#59Modular decoupled crossbar for on-chip router
#60Hierarchical reconfigurable computer architecture
#61Power supply control for a processing device, array-type processing device,and information processing system, and control method thereof
#62Embedding global and collective in a torus network with message class map based tree path selection
#63Scheduling tasks to configurable processing cores based on task requirements and specification
#64Storage device
#65Execution engine for executing single assignment programs with affine dependencies
#66Multiprocessor system with improved secondary interconnection network
#67Direct network having plural distributed connections to each resource
#68Parallel computing system and control method of parallel computing system
#69Distributed mesh-based memory and computing architecture
#70Network topology for a scalable multiprocessor system
#71Job management apparatus and job management method
#72Method and system for converting a single-threaded software program into an application-specific supercomputer
#73Managing chip multi-processors through virtual domains
#74Communicaton across shared mutually exclusive direction paths between clustered processing elements
#75Massively parallel supercomputer
#76On-chip router and multi-core system using the same
#77Deadlock prevention in direct networks of arbitrary topology
#78MULTIPROCESSING COMPUTING WITH DISTRIBUTED EMBEDDED SWITCHING
#79System and method for data exchange in multiprocessor computer systems
#80Multi-petascale highly efficient parallel supercomputer
#81Time division multiplexing based arbitration for shared optical links
#82Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders
#83Distributed parallel messaging for multiprocessor systems
#84Zone routing in a torus network
#85Opcode counting for performance measurement
#86Deadlock prevention in direct networks of arbitrary topology
#87Local rollback for fault-tolerance in parallel computing systems
#88Conditional load and store in a shared memory
#89Heap/stack guard pages using a wakeup unit
#90Deadlock-free class routes for collective communications embedded in a multi-dimensional torus network
#91Hierarchical reconfigurable computer architecture
#92Hierarchical passive networks
#93Simplifying and speeding the management of intra-node cache coherence
#94Routing image data across on-chip networks
#95Apparatus, method, and medium for controlling transmission of data
#96DATA PROCESSING DEVICE AND METHOD
#97Memory network methods, apparatus, and systems
#98Globally unique transaction identifiers
#99Priority Encoders
#100Converting a data placement between memory banks and an array processing section
#101Mesh network
#102Managing coherence via put/get windows
#103Execution engine for executing single assignment programs with affine dependencies
#104System and method for data exchange in multiprocessor computer systems
#105Massively parallel supercomputer
#106Data processing device and method
#107Data processing device and method
#108Network topology for a scalable multiprocessor system
#109Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture
#110Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture
#111Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture
#112System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture
#113System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture
#114Data capture technique for high speed signaling
#115Multiprocessor node controller circuit and method
#116Processor communication tokens
#117Method and apparatus for using port communications to switch processor modes
#118Routing data packets with hint bit for each six orthogonal directions in three dimensional torus computer system set to avoid nodes in problem list
#119Efficient implementation of multidimensional fast fourier transform on a distributed-memory parallel multi-node computer
#120System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels
#121Collective network for computer structures
#122Optimized scalable network switch
#123Twisted and wrapped array organized into clusters of processing elements
#124Reduction processing method for parallel computer, and parallel computer
#125Processor organized in clusters of processing elements and cluster interconnections by a clustering process
#126Data processing device and method
#127Managing coherence via put/get windows
#128Network topology for a scalable multiprocessor system
#129System and method for vector-parallel multiprocessor communication
#130Methods for routing packets on a linear array of processors
#131Globally unique transaction identifiers
#132Multiprocessor data processing system having scalable data interconnect and data routing mechanism
#133Method and system of interconnecting processors of a parallel computer to facilitate torus partitioning
#134Multi-dimensional lattice network
#135Multiprocessor node controller circuit and method
#136Reconfigurable streaming processor for security computations
#137Frequency band control algorithm