190460 ⎘
Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising a single central processing unit System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
VECTOR PROCESSING CIRCUIT AND VECTOR PROCESSING METHOD WITH REUSED CALCULATION CIRCUIT
#2GENERAL-PURPOSE CONTROL BOARD
#3POST-SYNCHRONIZATION OPERATIONS IN MULTI-TILE PROCESSOR COMPUTING
#4MAINBOARD, PROCESSOR BOARD AND COMPUTING SYSTEM
#5LOAD REDUCED MEMORY MODULE
#6GLOBALS BLOCKS IN REPLICATED BLOCK ARRAYS
#7Load reduced memory module
#8Chipset Attached Random Access Memory
#9SCALABLE 2.5D INTERFACE CIRCUITRY
#10FPGA-based USB 3.0/3.1 control system
#11Systems and methods to configure front panel header
#12BOARD DEVICE OF SINGLE BOARD COMPUTER
#13Load reduced memory module
#14Scalable 2.5D interface circuitry
#15Modular system for internet of things and method of assembling the same
#16Load reduced memory module
#17Scalable 2.5D interface circuitry
#18Scalable 2.5D interface circuitry
#19COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN PROGRAM FOR DETERMINING FPGA IMPLEMENTATION, METHOD FOR DETERMINING FPGA IMPLEMENTATION, AND INFORMATION PROCESSING APPARATUS
#20Load reduced memory module
#21Scalable 2.5D interface circuitry
#22Convolutional neural networks on hardware accelerators
#23Heterogeneous miniaturization platform
#24Computing system with hardware reconfiguration mechanism and method of operation thereof
#25Load reduced memory module
#26Adaptive routing to avoid non-repairable memory and logic defects on automata processor
#27Computer system and motherboard thereof
#28Multi-direction connectable electronic module and modular electronic building system
#29ENCODER WITH TOUCH SCREEN
#30Methods and apparatus for controlling interface circuitry
#31Load reduced memory module
#32Heterogeneous miniaturization platform
#33BOARD MANAGEMENT CONTROLLER PERIPHERAL CARD, HOST SYSTEM WITH THE SAME, AND METHOD FOR MANAGING HOST PERIPHERAL MEMBER BY THE SAME
#34Adaptive routing to avoid non-repairable memory and logic defects on automata processor
#35Deep neural network processing on hardware accelerators with stacked memory
#36Combinations of removable workload optimized modules for implementing different application workloads
#37Method and apparatus for server platform architectures that enable serviceable nonvolatile memory modules
#38Server on a chip and node cards comprising one or more of same
#39Node card management in a modular and large scalable server system
#40Node card utilizing a same connector to communicate pluralities of signals
#41Load reduced memory module
#42Load reduced memory module
#43SERVER ON A CHIP AND NODE CARDS COMPRISING ONE OR MORE OF SAME
#44Data processing system having power capping function in response to output state of power supply module
#45Node card management in a modular and large scalable server system
#46Arbitrating usage of serial port in node card of scalable and modular servers
#47Computing system with hardware reconfiguration mechanism and method of operation thereof
#48COMPUTING SYSTEM WITH HARDWARE RECONFIGURATION MECHANISM AND METHOD OF OPERATION THEREOF
#49Computing system with hardware scheduled reconfiguration mechanism and method of operation thereof
#50Computing system with hardware bus management and method of operation thereof
#51Computing system with data and control planes and method of operation thereof
#52Computing system with switching mechanism and method of operation thereof
#53Blade server apparatus
#54Data processing system having power capping function in response to output state of power supply module
#55MULTI-SCREEN SIGNAL PROCESSING DEVICE AND MULTI-SCREEN SYSTEM
#56Storage system with a memory blade that generates a computational result for a storage device
#57METHOD OF SHARING BASIC INPUT OUTPUT SYSTEM, AND BLADE SERVER AND COMPUTER USING THE SAME
#58Flexible interconnect port connection
#59Dynamic FPGA re-configuration using a virtual FPGA controller
#60Scalable 2.5D interface circuitry