190462 ⎘
Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising a single central processing unit; System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package On-chip cache; Off-chip memory
SORTING VECTOR ELEMENTS USING A MAPPING OF ELEMENTS
#2METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MULTIPLICATION
#3Permutation for Vector Operations
#4Multiple Multiplication Units in a Data Path
#5Method and Apparatus for Vector Sorting using Vector Permutation Logic
#6TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASIDE BUFFER READ
#7DETECTING INFINITE LOOPS IN A PROGRAMMABLE ATOMIC TRANSACTION
#8TOWER LIGHT DYNAMIC REGISTER POPULATION ENGINE PARSING UNIQUE FIELD-GENERATED PERFORMANCE STRING
#9TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EXECUTION
#10WAVEFORM-AWARE MIXED SIGNAL MEASUREMENT SYSTEM FOR BUS TRAFFIC REDUCTION IN SYSTEM-ON-A-CHIP DEVICES
#11FAST COMPUTE DIE ICC LIMIT TECHNIQUES
#12METHOD AND APPARATUS FOR VECTOR PERMUTATION
#13PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
#14Multiple system-on-chip arrangement for vehicle computing systems
#15METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS
#16SORTING VECTOR ELEMENTS USING A COUNT VALUE
#17Vector Based Matrix Multiplication
#18METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MULTIPLICATION
#19Method and Apparatus for Dual Issue Multiply Instructions
#20DETECTING INFINITE LOOPS IN A PROGRAMMABLE ATOMIC TRANSACTION
#21Multiple Multiplication Units in a Data Path
#22Runtime reconfigurable compression format conversion with bit-plane granularity
#23METHOD FOR MEASURING PERFORMANCE OF NEURAL PROCESSING DEVICE AND DEVICE FOR MEASURING PERFORMANCE
#24Method and Apparatus for Vector Sorting using Vector Permutation Logic
#25METHOD FOR OPTIMIZING MATRIX MULTIPLICATION OPERATION ON SYSTEM ON CHIP, AND RELATED PRODUCT
#26Tracking streaming engine vector predicates to control processor execution
#27Method and apparatus for dual issue multiply instructions
#28Method for measuring performance of neural processing device and device for measuring performance
#29HARDWARE ACCELERATION OF REINFORCEMENT LEARNING WITHIN NETWORK DEVICES
#30Method and apparatus for permuting streamed data elements
#31Data link stability detection using computer vision-based data eye analysis
#32METHOD AND APPARATUS TO SORT A VECTOR FOR A BITONIC SORTING ALGORITHM
#33Detecting infinite loops in a programmable atomic transaction
#34Memory system and SoC including linear address remapping logic
#35Method and apparatus for vector sorting
#36Method and apparatus for vector sorting using vector permutation logic
#37Detecting infinite loops in a programmable atomic transaction
#38Method for starting a system-on-a-chip without read only memory, system on-a- chip without read only memory and headphone
#39System on chip including secure processor and semiconductor system including the same
#40Method and apparatus for vector based matrix multiplication
#41Method and apparatus for dual issue multiply instructions
#42Method and apparatus for dual multiplication units in a data path
#43Method and apparatus to sort a vector for a bitonic sorting algorithm
#44Method and apparatus for permuting streamed data elements
#45Method and apparatus for vector permutation
#46Highly integrated scalable, flexible DSP megamodule architecture
#47Tracking streaming engine vector predicates to control processor execution
#48Two address translations from a single table look-aside buffer read
#49Memory system and SOC including linear address remapping logic
#50Address interleaving for machine learning
#51NEURAL NETWORK COMPUTING METHOD, SYSTEM AND DEVICE THEREFOR
#52Configurable heterogeneous AI processor with distributed task queues allowing parallel task execution
#53On-chip heterogeneous AI processor with distributed tasks queues allowing for parallel task execution
#54Method, apparatus and system for handling non-posted memory write transactions in a fabric
#55Memory system and SoC including linear address remapping logic
#56Memory system and SoC including linear address remapping logic
#57Hardware for supporting time triggered load anticipation in the context of a real time OS
#58Configurable peripherals
#59Neural network processing
#60Multiple transaction data flow control unit for high-speed interconnect
#61Method and apparatus for vector permutation
#62Cache partitioning in a multicore processor
#63Efficient virtual I/O address translation
#64End-to-end quality-of-service in a network-on-chip
#65Computing system with hardware reconfiguration mechanism and method of operation thereof
#66Multiple transaction data flow control unit for high-speed interconnect
#67Common platform for one-level memory architecture and two-level memory architecture
#68Tracking streaming engine vector predicates to control processor execution
#69COMPUTER PROCESSING UNIT (CPU) ARCHITECTURE FOR CONTROLLED AND LOW POWER SAVE OF CPU DATA TO PERSISTENT MEMORY
#70Using a first-in-first-out (FIFO) wraparound address lookup table (ALT) to manage cached data
#71Caching for heterogeneous processors
#72Memory system and SoC including linear address remapping logic
#73Determination of idle power state
#74System and method for booting within a heterogeneous memory environment
#75On-chip data partitioning read-write method, system, and device
#76CONCURRENT CACHE MEMORY ACCESS
#77Collated multi-image check in system-on-chips
#78Bus encoding using on-chip memory
#79Method, apparatus and system for handling non-posted memory write transactions in a fabric
#80ELECTRONIC DEVICE AND DATA TRANSFER METHOD THEREOF
#81Memory device sensing circuit
#82System on chip integrity verification method and system
#83Using data pattern to mark cache lines as invalid
#84Enabling system low power state when compute elements are active
#85Frequency adjustment method, System-On-Chip, and terminal
#86Cache partitioning in a multicore processor
#87SNOOP OPTIMIZATION FOR MULTI-PORTED NODES OF A DATA PROCESSING SYSTEM
#88Byte and nibble sort instructions that produce sorted destination register and destination index mapping
#89Memory system and SoC including linear address remapping logic
#90Hardware power-on initialization of an SoC through a dedicated processor
#91Common platform for one-level memory architecture and two-level memory architecture
#92Method, apparatus, system for continuous automatic tuning of code regions
#93Caching for heterogeneous processors
#94Efficient virtual I/O address translation
#95Low-layer memory for a computing platform
#96Multiple transaction data flow control unit for high-speed interconnect
#97Photonics-Optimized Processor System
#98Photonics-optimized processor system
#99System on-chip and electronic device including the same
#100GUARANTEED QUALITY OF SERVICE IN SYSTEM-ON-A-CHIP UNCORE FABRIC
#101Caching for heterogeneous processors
#102Method, apparatus and system for modular on-die coherent interconnect for packetized communication
#103Caching for heterogeneous processors
#104System and method for analyzing a QC strategy for releasing results
#105Performing collective operations in a distributed processing system
#106Performing collective operations in a distributed processing system
#107Receive queue models to reduce I/O cache consumption
#108Systems and methods for large-scale randomized optimization for problems with decomposable loss functions
#109Systems and methods for large-scale randomized optimization for problems with decomposable loss functions
#110System and method for determining an optimum QC strategy for immediate release results
#111Method and apparatus for session bandwidth estimation and rate control
#112Computing system with hardware reconfiguration mechanism and method of operation thereof
#113COMPUTING SYSTEM WITH HARDWARE RECONFIGURATION MECHANISM AND METHOD OF OPERATION THEREOF
#114Computing system with hardware scheduled reconfiguration mechanism and method of operation thereof
#115Computing system with hardware bus management and method of operation thereof
#116Computing system with data and control planes and method of operation thereof
#117Computing system with switching mechanism and method of operation thereof
#118Communications system including trusted server to verify a redirection request and associated methods
#119CONFIGURING CONNECTION AGENTS
#120Caching for heterogeneous processors
#121Low power, high performance, heterogeneous, scalable processor architecture
#122Heterogeneous processors sharing a common cache
#123System on chip with reconfigurable SRAM
#124Programmable Processor Architecture
#125Thread optimized multiprocessor architecture
#126Heterogeneous processors sharing a common cache
#127Heterogeneous processors sharing a common cache
#128Programmable processor architecture hirarchical compilation
#129Low power, high performance, heterogeneous, scalable processor architecture
#130Multi-core multi-thread processor