ClassID:

190464

G06F15/7817 - CPC Classification

Classification description:

Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising a single central processing unit; System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package Specially adapted for signal processing, e.g. Harvard architectures

Recent Application in this class:
#1
20260127135
2026-05-07

SIGNAL PROCESSING AND TRANSMISSION IN ELECTRONIC CIRCUITS

#2
20250342136
2025-11-06

CHIPLET COMPOSABILITY

#3
20250272096
2025-08-28

Enhanced Harvard Architecture Reduced Instruction Set Computer (RISC) with Debug Mode Access of Instruction Memory within a Unified Memory Space

#4
20250252065
2025-08-07

MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK

#5
20250209035
2025-06-26

MONOLITHICALLY INTEGRATED SYSTEM ON CHIP FOR SILICON PHOTONICS

#6
20250077469
2025-03-06

VOICE CHIP IMPLEMENTATION METHOD, VOICE CHIP, AND RELATED DEVICE

#7
20240256472
2024-08-01

Multiprocessor system with improved secondary interconnection network

#8
20230409517
2023-12-21

DSP encapsulation

#9
20230251992
2023-08-10

Monolithically integrated system on chip for silicon photonics

#10
20220413544
2022-12-29

Low power system on chip

#11
20220358080
2022-11-10

Silicon photonics based module for executing peer-to-peer transactions

#12
20220327009
2022-10-13

Message passing circuitry and method

#13
20220309029
2022-09-29

Tensor partitioning and partition access order

#14
20220283982
2022-09-08

Monolithically integrated system on chip for silicon photonics

#15
20220271753
2022-08-25

Clock tree, hash engine, computing chip, hash board and data processing device

#16
20220197854
2022-06-23

Reconfigurable System-On-Chip

#17
20210409286
2021-12-30

Artificial intelligence of things (AIoT) development system and wearable device having the same

#18
20210073450
2021-03-11

Tool to create a reconfigurable interconnect framework

#19
20210049124
2021-02-18

Monolithically integrated system on chip for silicon photonics

#20
20200341914
2020-10-29

Multiprocessor system with improved secondary interconnection network

#21
20200327093
2020-10-15

Silicon photonics based module for storing cryptocurrency and executing peer-to-peer transaction

#22
20200311018
2020-10-01

System, apparatus and method for adaptive interconnect routing

#23
20200272779
2020-08-27

Reconfigurable interconnect

#24
20200242073
2020-07-30

Monolithically integrated system on chip for silicon photonics

#25
20190377840
2019-12-12

Tool to create a reconfigurable interconnect framework

#26
20190354507
2019-11-21

Monolithically integrated system on chip for silicon photonics

#27
20190340314
2019-11-07

Reconfigurable interconnect

#28
20190332571
2019-10-31

Method and system for enumerating digital circuits in a system-on-a-chip (SOC)

#29
20190332570
2019-10-31

Method and system for enumerating digital circuits in a system-on-a-chip (SOC)

#30
20190258598
2019-08-22

Single-chip control module for an integrated system-on-a-chip for silicon photonics

#31
20190213152
2019-07-11

Software-defined device interface system and method

#32
20190205285
2019-07-04

Monolithically integrated system on chip for silicon photonics

#33
20190155761
2019-05-23

Multiprocessor system with improved secondary interconnection network

#34
20190129493
2019-05-02

Memory access management for low-power use cases of a system on chip via secure non-volatile random access memory

#35
20190108161
2019-04-11

Silicon photonics based module for storing cryptocurrency and executing peer-to-peer transaction

#36
20190018822
2019-01-17

Method and apparatus for constructing multivalued microprocessor

#37
20190012287
2019-01-10

Microcontroller programmable system on a chip

#38
20180349180
2018-12-06

Method and apparatus for scheduling arbitration among a plurality of service requestors

#39
20180336147
2018-11-22

APPLICATION PROCESSOR INCLUDING COMMAND CONTROLLER AND INTEGRATED CIRCUIT INCLUDING THE SAME

#40
20180329852
2018-11-15

Single-chip control module for an integrated system-on-a-chip for silicon photonics

#41
20180232324
2018-08-16

Multi-port multi-sideband-GPIO consolidation technique over a multi-drop serial bus

#42
20180189642
2018-07-05

Configurable accelerator framework including a stream switch having a plurality of unidirectional stream links

#43
20180189641
2018-07-05

Hardware accelerator engine

#44
20180189424
2018-07-05

Tool to create a reconfigurable interconnect framework

#45
20180189229
2018-07-05

Deep convolutional network heterogeneous architecture

#46
20180189215
2018-07-05

Reconfigurable interconnect

#47
20180081856
2018-03-22

Monolithically integrated system on chip for silicon photonics

#48
20180067888
2018-03-08

Single-chip control module for an integrated system-on-a-chip for silicon photonics

#49
20180032466
2018-02-01

Single-chip control module for an integrated system-on-a-chip for silicon photonics

#50
20170262407
2017-09-14

Reconfigurable data interface unit for compute systems

#51
20170228327
2017-08-10

Serial communication link with optimal transfer latency

#52
20170185558
2017-06-29

Microcontroller programmable system on a chip

#53
20170177536
2017-06-22

Microcontroller programmable system on a chip

#54
20170161229
2017-06-08

Method and system for enumerating digital circuits in a system-on-a-chip (SOC)

#55
20170161225
2017-06-08

Method and system for enumerating digital circuits in a system-on-a-chip (SOC)

#56
20170161214
2017-06-08

Multiprocessor system with improved secondary interconnection network

#57
20170154007
2017-06-01

Logic-based decoder for crosstalk-harnessed signaling

#58
20170124022
2017-05-04

Monolithically integrated system on chip for silicon photonics

#59
20170010999
2017-01-12

Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus

#60
20170010987
2017-01-12

Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus

#61
20160124899
2016-05-05

MULTI-CHIP PACKAGED FUNCTION INCLUDING A PROGRAMMABLE DEVICE AND A FIXED FUNCTION DIE AND USE FOR APPLICATION ACCELERATION

#62
20160034411
2016-02-04

Subsystem Peripheral Ownership Scheduling and Reconfiguration for Highly Integrated System on Chips

#63
20120331028
2012-12-27

Processor for performing multiply-add operations on packed data

#64
20120216018
2012-08-23

Processor for performing multiply-add operations on packed data

#65
20120023281
2012-01-26

Single-chip microcomputer

#66
20110283057
2011-11-17

Microcontroller programmable system on a chip with programmable interconnect

#67
20110264895
2011-10-27

Method and apparatus for performing multiply-add operations on packed data

#68
20100306502
2010-12-02

Digital signal processor having a plurality of independent dedicated processors

#69
20090265409
2009-10-22

Processor for performing multiply-add operations on packed data

#70
20080294873
2008-11-27

Microcomputer

#71
20080263228
2008-10-23

Single-chip microcomputer

#72
20060224859
2006-10-05

Microcomputer

#73
18217185
2026-02-03

Signal processing and transmission in electronic circuits

#74
17803388
2024-02-06

Super system on chip

#75
17216650
2022-06-21

Multi-headed multi-buffer for buffering data for processing

#76
17216647
2021-12-21

Tensor partitioning and partition access order

#77
16108041
2019-08-13

Efficient cognitive signal denoising with sparse output layers

#78
15463993
2019-08-06

Memory-mapped state bus for integrated circuit