190468 ⎘
Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
MULTI-CORE CHIP, INTEGRATED CIRCUIT APPARATUS, AND BOARD CARD AND MANUFACTURING PROCEDURE METHOD THEREFOR
#2Data processing method and apparatus, and related product
#3Microprocessor with dynamically adjustable bit width for processing data
#4Microprocessor for neural network computing and processing method of macroinstruction
#5Microprocessor with booth multiplication
#6Microprocessor with booth multiplication
#7Method for supervising and initializing ports
#8Device for supervising and initializing ports
#9Power supply system
#10Processor including first transistor and second transistor
#113-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits
#123-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits
#13Semiconductor device
#14Direct interthread communication dataport pack/unpack and load/save
#15Processor for enabling inter-sequencer communication following lock competition and accelerator registration
#16System and apparatus for group floating-point inflate and deflate operations
#17System and apparatus for group floating-point inflate and deflate operations
#18SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT ARITHMETIC OPERATIONS
#19Single chip protocol converter
#20PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES
#21Semiconductor device
#22Semiconductor device and method for manufacturing semiconductor device
#23Semiconductor device
#24Apparatus and method for enabling inter-sequencer communication following lock competition and accelerator registration
#25Data processing system and image processing system
#26Single-Chip Computer and Tachograph
#27Flexible results pipeline for processing element
#28Method and apparatus for performing improved group instructions
#29Multi-die processor
#30Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration
#31Single chip protocol converter
#32Datapipe interpolation device
#33MAC ARCHITECTURE FOR PIPELINED ACCUMULATIONS
#34Semiconductor device
#35Method and software for group data operations
#36Data processing system and image processing system
#37System and apparatus for group data operations
#38Method and Apparatus for Performing Group Instructions
#39Semiconductor device
#40Method and software for group floating-point arithmetic operations
#41System and apparatus for group floating-point arithmetic operations
#42Hard macro with configurable side input/output terminals, for a subsystem
#43Method and Apparatus for Programmable Processor
#44Method and Apparatus for Performing Data Handling Operations
#45Method and Apparatus for Performing Improved Data Handling Operations
#46Method and apparatus for performing improved group floating-point operations
#47Method and Apparatus for Improved Programmable Processor
#48Method and Apparatus for Performing Group Floating-Point Operations
#49System on chip IC with subsystem of multiple processing cores switch coupled to network protocol device and bus bridge to local system bus
#50Common analog interface for multiple processor cores
#51Semiconductor device and mobile phone using the same
#52Processor
#53Processor automatically performing processor ID setting and path setting and method of configuring multiprocessor
#54Real-time processor
#55Chip processors with integrated I/O
#56Processor and a method in the processor, the processor comprising a programmable pipeline and at least one interface engine
#57Method and apparatus for pipelined processing of data packets
#58Configurable microprocessor architecture incorporating direct execution unit connectivity
#59Integrated circuit
#60Multi-die processor
#61Semiconductor integrated circuit device
#62System resource router
#63Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
#64Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus