PERFORMANCE EVALUATOR FOR A HETEROGENOUS HARDWARE PLATFORM

DYNAMIC PROCESSING MEMORY CORE ON A SINGLE MEMORY CHIP

Dynamic processing memory core on a single memory chip

Power efficient memory value updates for arm architectures

INTEGRATED CIRCUIT

Architecture to support synchronization between core and inference engine for machine learning

Compute-in-memory macro device and electronic device

METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR COMPUTE-IN-MEMORY MACRO ARRANGEMENT, AND ELECTRONIC DEVICE APPLYING THE SAME

UNIVERSAL SYNCHRONOUS FIFO IP CORE FOR FIELD PROGRAMMABLE GATE ARRAYS

Power management circuit and system thereof

SMID processing unit performing concurrent load/store and ALU operations

Chip and interface conversion device

Architecture to support synchronization between core and inference engine for machine learning

Technologies for providing a scalable architecture for performing compute operations in memory

Multiple programmable hardware-based on-chip password

Technologies for providing a scalable architecture for performing compute operations in memory

Processor for Implementing Non-Arithmetic Functions

Processor For Implementing Mathematical Functions or Models

Secure system on chip

Caching for heterogeneous processors

Data read-write scheduler and reservation station for vector operations

Data read-write scheduler and reservation station for vector operations

Secure semiconductor chip and operating method thereof

Secure semiconductor chip and operating method thereof

Data read-write scheduler and reservation station for vector operations

Sensor data generation and response handling stack

MICROCONTROLLER WITH A DIAGNOSIS MODULE AND METHOD FOR ACCESSING SAID MODULE OF SAID MICROCONTROLLER

Arbitrary waveform generator based on instruction architecture

Microcontroller and electronic control unit

Processor comprising three-dimensional memory (3D-M) array

Control apparatus, integrated circuit and management method for stack

Caching for heterogeneous processors

Caching for heterogeneous processors

System-on-chip design structure

Caching for heterogeneous processors

System-on-chip design structure and method

Interface logic for a multi-core system-on-a-chip (SoC)

Multi-band interconnect for inter-chip and intra-chip communications

System on chip with reconfigurable SRAM

Data processing unit including a scalar processing unit and a heterogeneous processor unit

Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program

Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode

Low power, high performance, heterogeneous, scalable processor architecture

Communication using integrated circuit interconnect circuitry

Data processing system and method for switching between heterogeneous accelerators

Tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms

Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetch

Stack processor using a ferroelectric random access memory (F-RAM) for both code and data space

Caching for heterogeneous processors

Programmable cryptographic integrated circuit

Method and apparatus for routing transactions through partitions of a system-on-chip

Single chip protocol converter

Processor on an Electronic Microchip Comprising a Hardware Real-Time Monitor

Multiple-core processor supporting multiple instruction set architectures

Processing architecture

Interface logic for a multi-core system-on-a-chip (SoC)

Reconfigurable elements

Methods and Systems for Managing Variable Delays in Packet Transmission

Low power, high performance, heterogeneous, scalable processor architecture

Integrated circuit with stacked computational units and configurable through vias

On-chip networks for flexible three-dimensional chip integration

Data processing system, data processing method, and apparatus

Hybrid optimized personal computer

Parallel processing and internal processors

Method and apparatus for hardware XML acceleration

Data processing apparatus and method of controlling the data processing apparatus

Microcontroller with integrated graphical processing unit

Multi-core stream processor having (N) processing units and (N+1) fetching units

Reconfigurable elements

Processor integrated circuit and product development method using the processing integrated circuit

Heterogeneous processors sharing a common cache

Programmable system on a chip for power-supply voltage and current monitoring and control

Distributed Processing Architecture With Scalable Processing Layers

Methods and systems for managing variable delays in packet transmission

Programmable system on a chip

Image sensor with scaler and image scaling method thereof

Microcontroller waveform generation

Reconfigurable wireless modem sub-circuits to implement multiple air interface standards

Energy efficient processing device

IC for handheld computing unit of a computing device

Multi-mode bit rate processor

Method and apparatus for performing improved group instructions

MULTI-PROCESSOR SYSTEM ON CHIP PLATFORM AND DVB-T BASEBAND RECEIVER USING THE SAME

Programmable system on a chip for power-supply voltage and current monitoring and control

RAPID CREATION AND CONFIGURATION OF MICROCONTROLLER PRODUCTS WITH CONFIGURABLE LOGIC DEVICES

Field programmable gate array and microcontroller system-on-a-chip

Multimedia processing in parallel multi-core computation architectures

Single chip protocol converter

TOKEN PROTOCOL

Clock-generator architecture for a programmable-logic-based system on a chip

SHARED MEMORY FOR MULTI-CORE PROCESSORS

Programmable system on a chip for temperature monitoring and control

System-on-Chip Apparatus with Time Shareable Memory and Method for Operating Such an Apparatus

Network core access architecture

System-on-a-chip integrated circuit including dual-function analog and digital inputs

System on chip with reconfigurable SRAM

Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor

Non-volatile memory architecture for programmable-logic-based system on a chip

Automata based storage and execution of application logic in smart card like devices

Task based debugger (transaction-event-job-trigger)

Integrated circuit device having state-saving and initialization feature

Programmable system on a chip

Programmable system on a chip for power-supply voltage and current monitoring and control

Multiple-core processor supporting multiple instruction set architectures

Programmable system on a chip

Programmable system on a chip for power-supply voltage and current monitoring and control

Reconfigurable data processing system

Programmable Processor Architecture

Network Processor

Programmable system on a chip for temperature monitoring and control

PROGRAMMABLE SYSTEM ON A CHIP

PROCESSOR HAVING MULTIPLE INSTRUCTION SOURCES AND EXECUTION MODES

Processor apparatus including specific signal processor core capable of dynamically scheduling tasks and its task control method

Method and apparatus for hardware XML acceleration

Bus system for integrated circuit

Superior cache processor landing zone to support multiple processors

System-on-a-chip integrated circuit including dual-function analog and digital inputs

Distributed processing architecture with scalable processing layers

Complex vector executing clustered SIMD micro-architecture DSP with accelerator coupled complex ALU paths each further including short multiplier/accumulator using two's complement

Non-volatile memory architecture for programmable-logic-based system on a chip

Method and apparatus to provide dynamic hardware signal allocation in a processor

Processor integrated circuit and product development method using the processor integrated circuit

Image sensor with scaler and image scaling method thereof

Integrated circuit including programmable logic and external-device chip-enable override control

Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor

Programmable system on a chip for power-supply voltage and current monitoring and control

Processing system

Heterogeneous processors sharing a common cache

Heterogeneous processors sharing a common cache

Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit

Processor condition sensing circuits, systems and methods

Programmable processor architecture hirarchical compilation

Low power, high performance, heterogeneous, scalable processor architecture

Multi-threaded processing design in architecture with multiple co-processors

Field programmable gate array and microcontroller system-on-a-chip

Programmable system on a chip

Method and system for dual-core processing

In-circuit configuration architecture for embedded configurable logic array

Information-processing apparatus and electronic equipment using thereof

Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus

Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

Multiple programmable hardware-based on-chip password

Hardware trace and introspection for productivity platform using a system-on-chip