190481 ⎘
Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture; Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS for pipeline reconfiguration
CONFIGURABLE LOGIC SYSTEM AND METHOD FOR PIPELINED DATA TRANSFER
#2COMPUTATIONAL NODES FUSION IN A RECONFIGURABLE DATA PROCESSOR
#3Reconfigurable Parallel Processing
#4Low latency nodes fusion in a reconfigurable data processor
#5Pipelined cognitive signal processor
#6Reconfigurable parallel processing
#7Reconfigurable parallel processing
#8Reconfigurable parallel processing with various reconfigurable units to form two or more physical data paths and routing data from one physical data path to a gasket memory to be used in a future physical data path as input
#9Policy handling for data pipelines
#10Reconfigurable parallel processing with a temporary data storage coupled to a plurality of processing elements (PES) to store a PE execution result to be used by a PE during a next PE configuration
#11Circular reconfiguration for reconfigurable parallel processor using a plurality of memory ports coupled to a commonly accessible memory unit
#12Shared memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit
#13Private memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit
#14Pipelining multi-directional reduction
#15Pipelined cognitive signal processor
#16PIPELINED CONFIGURABLE PROCESSOR
#17Reconfigurable parallel processing
#18Customizing operator nodes for graphical representations of data processing pipelines
#19Information processing apparatus and information processing method for process order in reconfigurable circuit
#20Processors and methods for pipelined runtime services in a spatial array
#21Shared memory access for a reconfigurable parallel processor with a plurality of chained memory ports
#22Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports
#23Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports
#24Reconfigurable parallel processor with a plurality of chained memory ports
#25Static shared memory access with one piece of input data to be reused for successive execution of one instruction in a reconfigurable parallel processor
#26Pipelined configurable processor
#27Information processing device, information processing method, information processing program, and recording medium
#28Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction
#29Pipelined configurable processor
#30COMPUTING APPARATUS BASED ON RECONFIGURABLE ARCHITECTURE AND MEMORY DEPENDENCE CORRECTION METHOD THEREOF
#31MULTI-PROCESSOR CHIP WITH SHARED FPGA EXECUTION UNIT AND A DESIGN STRUCTURE THEREOF
#32Data processing apparatus
#33Configuration of a deep vector engine using an opcode table, control table, and datapath table
#34Defect repair for a reconfigurable data processor for homogeneous subarrays
#35Method of and device for processing data using a pipeline of processing blocks