190485 ⎘
Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture; Runtime interface, e.g. data exchange, runtime control Reconfigurable logic embedded in CPU, e.g. reconfigurable unit
HARDWARE ACCELERATOR WITH CONFIGURABLE TENSOR OPERATION PIPELINE
#2PROCESSING OF ETHERNET PACKETS AT A PROGRAMMABLE INTEGRATED CIRCUIT
#3DATA PROCESSING SYSTEM WITH LINK-BASED RESOURCE ALLOCATION FOR RECONFIGURABLE PROCESSORS
#4APPARATUS INCLUDING RECONFIGURABLE INTERFACE AND METHODS OF MANUFACTURING THE SAME
#5ARITHMETIC OPERATION DEVICE, TESTING METHOD
#6Processing of ethernet packets at a programmable integrated circuit
#7Reconfigurable computing chip
#8Apparatus including reconfigurable interface and methods of manufacturing the same
#9Processor chip, dongle device, and operation method
#10Performance estimation-based resource allocation for reconfigurable architectures
#11UNIVERSAL SYNCHRONOUS FIFO IP CORE FOR FIELD PROGRAMMABLE GATE ARRAYS
#12Tensor partitioning and partition access order
#13Interconnect-based resource allocation for reconfigurable processors
#14Processing of ethernet packets at a programmable integrated circuit
#15APPARATUS FOR THE SPECTROSCOPIC DETERMINATION OF THE BINDING KINETICS OF AN ANALYTE
#16Compile time logic for inserting a buffer between a producer operation unit and a consumer operation unit in a dataflow graph
#17Three-dimensional stacked programmable logic fabric and processor design architecture
#18Configuration of hardware devices
#19DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD
#20Programmable Fabric-Based Instruction Set Architecture for a Processor
#21Processing of ethernet packets at a programmable integrated circuit
#22Performance estimation-based resource allocation for reconfigurable architectures
#23Processing of ethernet packets at a programmable integrated circuit
#24Reconfigurable computing appliance
#25Integration of a programmable device and a processing system in an integrated circuit package
#26Selectable peripheral logic in programmable apparatus
#27Selectable peripheral logic in programmable apparatus
#28Selectable peripheral logic in programmable apparatus
#29Apparatus and method for a hybrid latency-throughput processor
#30Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator
#31Methods and apparatus to improve data training of a machine learning model using a field programmable gate array
#32Selectable peripheral logic in programmable apparatus
#33Reconfigurable processor and timing control method thereof
#34True random generator (TRNG) in ML accelerators for NN dropout and initialization
#35Processor with memory controller including dynamically programmable functional unit
#36Processor with an expandable instruction set architecture for dynamically configuring execution resources
#37Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
#38Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces
#39Apparatus and method for a hybrid latency-throughput processor
#40System on a chip comprising reconfigurable resources for multiple compute sub-systems
#41Processor arranged to operate as a single-threaded (nX)-bit processor and as an n-threaded X-bit processor in different modes of operation
#42Incorporating a spatial array into one or more programmable processor cores
#43Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match
#44Apparatus and method for a hybrid latency-throughput processor
#45Reconfigurable processor for parallel processing and operation method of the reconfigurable processor
#46DYNAMICALLY RECONFIGURABLE PROCESSOR AND METHOD OF OPERATING THE SAME
#47Re-programming programmable hardware devices without system downtime
#48Re-programming programmable hardware devices without system downtime
#49RECONFIGURABLE PROCESSOR, APPARATUS, AND METHOD FOR CONVERTING CODE
#50Reconfigurable processor with routing node frequency based on the number of routing nodes
#51DATA PROCESSING SYSTEM AND CONTROL METHOD THEREOF
#52Defect repair for a reconfigurable data processor for homogeneous subarrays
#53Lossless tiling in convolution networks—read-modify-write in backward pass
#54Tensor partitioning and partition access order
#55Resource allocation for reconfigurable processors
#56Packet identification (ID) assignment for routing network
#57Virtual FPGA management and optimization system
#58Selectable peripheral logic in programmable apparatus
#59Memory circuits and methods for distributed memory hazard detection and error recovery