190491 ⎘
Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors Three-dimensional arrays or hypercubes
TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY
#2Three-Dimensional Modular Asynchronous Parallel Computer and Methods of Construction Therefor
#33D DATAFLOW ARCHITECTURE FOR A COMPUTING DEVICE
#4Discrete Three-Dimensional Processor
#5Discrete Three-Dimensional Processor
#6Discrete Three-Dimensional Processor
#7Discrete Three-Dimensional Processor
#8SUPER SYSTEM ON CHIP
#9TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY
#10NEURAL NETWORK ACCELERATOR
#11Discrete Three-Dimensional Processor
#12Discrete Three-Dimensional Processor
#13Discrete three-dimensional processor
#14Discrete three-dimensional processor
#15Discrete three-dimensional processor
#16Discrete Three-Dimensional Processor
#17Discrete three-dimensional processor
#18Discrete three-dimensional processor
#19Computational storage systems and methods
#20Discrete three-dimensional processor
#21Compute accelerator with 3D data flows
#22Discrete three-dimensional processor
#23Unsupervised clustering in quantum feature spaces using quantum similarity matrices
#24Technologies for providing a scalable architecture for performing compute operations in memory
#25Discrete three-dimensional processor
#26Visualizing or interacting with a quantum processor
#27Visualizing or interacting with a quantum processor
#28Processor for calculating mathematical functions in parallel
#29Heterogeneous miniaturization platform
#30High performance computing (HPC) node having a plurality of switch coupled processors
#31Technologies for providing a scalable architecture for performing compute operations in memory
#32Apparatus and Methods of Providing Efficient Data Parallelization for Multi-Dimensional FFTs
#33Die and package
#34Die and package
#35Parallel processing apparatus, parallel computing method, and recording medium storing parallel computing program
#36Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods
#37SYSTEMS, DEVICES, ARTICLES, AND METHODS FOR QUANTUM PROCESSOR ARCHITECTURE
#38Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
#39Heterogeneous miniaturization platform
#40Network topology system and method
#41Efficient calibration of a low power parallel data communications channel
#42Faulty core recovery mechanisms for a three-dimensional network on a processor array
#43Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array
#44Faulty core recovery mechanisms for a three-dimensional network on a processor array
#45High performance computing (HPC) node having a plurality of switch coupled processors
#46Incorporating a spatial array into one or more programmable processor cores
#47Hierarchical reconfigurable computer architecture
#48Faulty core recovery mechanisms for a three-dimensional network on a processor array
#49Efficient calibration of a low power parallel data communications channel
#50INFORMATION PROCESSING SYSTEM, ROUTING METHOD AND PROGRAM
#51Three-dimensional permute unit for a single-instruction multiple-data processor
#52High performance computing (HPC) node having a plurality of switch coupled processors
#53Geodesic Massively Parallel Computer.
#54Scheduling computation processes including all-to-all communications (A2A) for pipelined parallel processing among plurality of processor nodes constituting network of n-dimensional space
#55Electronic chip and integrated circuit including a split routing unit having first-level routers for intra-layer transmissions and second-level routers for inter-layer transmissions and transmissions to the processing units
#56Parallel computing system and communication control program
#57Hierarchical reconfigurable computer architecture
#58DATA PROCESSING DEVICE AND METHOD
#59Data processing device and method
#60Data processing device and method
#61Ultra-scalable supercomputer based on MPU architecture
#62Operational dynamics of three dimensional intelligent system on a chip
#63Interconnect architecture in three dimensional network on a chip
#64Method and Apparatus for Operating a Massively Parallel Computer System to Utilize Idle Processor Capability at Process Synchronization Points
#65Multiple level minimum logic network
#66Data processing device and method
#67Coupling processors to each other for high performance computing (HPC)
#68Fast determination of workgroup batches from multi-dimensional kernels
#69Distributed batch matching of videos with dynamic resource allocation based on global score and prioritized scheduling score in a heterogeneous computing environment