190492 ⎘
Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors Associative processors
DATA-PARALLEL EXECUTION ON RECONFIGURABLE PROCESSORS
#2PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO
#3Auto-Discovery Module for the Discovery of Reconfigurable Processors in a Pool of Heterogeneous Reconfigurable Processors
#4HIGH PERFORMANCE PROCESSOR FOR LOW-WAY AND HIGH-LATENCY MEMORY INSTANCES
#5IMPLEMENTING HETEROGENEOUS INSTRUCTION SETS IN HETEROGENEOUS COMPUTE ARCHITECTURES
#6Cable pair concurrent servicing
#7System of Heterogeneous Reconfigurable Processors for the Data-Parallel Execution of Applications
#8System for executing an application on heterogeneous reconfigurable processors
#9Processing system for a vehicle
#10COMPILER FOR A PARALLEL PROCESSOR
#11Accelerator and electronic device including the same
#12Apparatus and method for dynamic control of microprocessor configuration
#13MEMORY-BASED DISTRIBUTED PROCESSOR ARCHITECTURE
#14Accelerator and electronic device including the same
#15Memory-based distributed processor architecture
#16Processing system with interspersed processors DMA-FIFO
#17Apparatus and method for dynamic control of microprocessor configuration
#18Mainboard and server
#19Memory-based distributed processor architecture
#20Processing system with interspersed processors with multi-layer interconnect
#21Flexible coupling of processor modules
#22Memory-based distributed processor architecture
#23Memory-based distributed processor architecture
#24Memory-based distributed processor architecture
#25Memory-based distributed processor architecture
#26Memory-based distributed processor architecture
#27Memory-based distributed processor architecture
#28Write-through detection for a memory circuit with an analog bypass portion
#29Processing system with interspersed processors with multi-layer interconnection
#30Processors, methods, and systems for debugging a configurable spatial accelerator
#31Processing system with interspersed processors with multi-layer interconnection
#32Single-chip multi-processor communication
#33Processing system with interspersed processors with multi-layer interconnection
#34Multi-core processor including a master core performing tasks involving operating system kernel-related features on behalf of slave cores
#35Processing system with interspersed processors DMA-FIFO
#36Multisystem and method of booting the same
#37Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture
#38External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit
#39Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture
#40Multiprocessor system having direct transfer function for program status information in multilink architecture
#41Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture
#42Scalable processing network for searching and adding in a content addressable memory