190498 ⎘
Digital computers in general ; Data processing equipment in general; Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors; Vector processors; Details on data register access Special arrangements thereof, e.g. mask or switch
GENERAL-PURPOSE SYSTOLIC ARRAY
#2NEOHARRY: HIGH-PERFORMANCE PARALLEL MULTI-LITERAL MATCHING ALGORITHM
#3General-purpose systolic array
#4General-purpose systolic array
#5Processor core design optimized for machine learning applications
#6METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX AND AN IMMEDIATE
#7Method and system for partial wavefront merger
#8Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices
#9Arithmetic unit
#10Memories and methods for performing vector atomic memory operations with mask control and variable data length and data unit size
#11Apparatus and method for vector compression
#12Hardware processors and methods for tightly-coupled heterogeneous computing
#13Methods and systems for fast set-membership tests using one or more processors that support single instruction multiple data instructions
#14Methods and systems for fast set-membership tests using one or more processors that support single instruction multiple data instructions
#15Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate
#16System and method of loop vectorization by compressing indices and data elements from iterations based on a control mask
#17Exception preserving parallel data processing of string and unstructured text
#18Multithreading in vector processors
#19Method and apparatus for performing a vector bit shuffle
#20Method and apparatus for performing a vector permute with an index and an immediate
#21Method and apparatus for efficiently managing architectural register state of a processor
#22Apparatus and method for vector compression
#23Data packet processing
#24Methods and systems for fast set-membership tests using one or more processors that support single instruction multiple data instructions
#25Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate
#26System and method of loop vectorization by compressing indexes and data elements from iterations based on a control mask
#27Vector move instruction controlled by read and write masks
#28Systems and methods of data extraction in a vector processor
#29APPARATUS AND METHOD FOR BROADCASTING FROM A GENERAL PURPOSE REGISTER TO A VECTOR REGISTER
#30Vector processing in an active memory device
#31Predication in a vector processor
#32Vector processing in an active memory device
#33Predication in a vector processor
#34Apparatus and method of vector unit sharing
#35Vector completion mask handling
#36Memories and methods for performing vector atomic memory operations with mask control and variable data length and data unit size
#37DYNAMICALLY-SELECTABLE VECTOR REGISTER PARTITIONING
#38Providing extended precision in SIMD vector arithmetic operations
#39Result data forwarding in parallel vector data processor based on scalar operation issue order
#40Two dimensional addressing of a matrix-vector register array
#41Vector processor and system for vector processing
#42Vector completion mask handling
#43Two dimensional addressing of a matrix-vector register array
#44Data buffer device, cache device, and data buffer control method
#45System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
#46Method and apparatus for producing an index vector for use in performing a vector permute operation
#47Providing extended precision in SIMD vector arithmetic operations
#48Arrangement, system and method for vector permutation in single-instruction multiple-data mircoprocessors
#49Two dimensional addressing of a matrix-vector register array
#50Core for a data processing engine in an integrated circuit
#51Constrained backup image defragmentation optimization within deduplication system