191119 ⎘
Indexing scheme relating to error detection, to error correction, and to monitoring Systems in which the redundancy can be transformed in increased performance
UTILIZING DATA PROCESSING UNITS TO OPTIMIZE PERFORMANCE OF AN ARTIFICAL INTELLIGENCE STORAGE SYSTEM
#2Data Processing Network for Performing Data Processing
#3STORAGE CLUSTER UTILIZING DIFFERING LOAD BALANCERS
#4IMPLEMENTING NATIVE SNAPSHOTTING FOR REDO-LOG FORMAT SNAPSHOTS
#5DATASET IMAGE CREATION
#6STORAGE SYSTEM ACCOMMODATING DIFFERING TYPES OF STORAGE
#7Independent communication pathways
#8Multilevel load balancing
#9Package On Package Memory Interface and Configuration With Error Code Correction
#10Configurable computer memory
#11Storage system, data copy control method, and recording medium
#12Distribution of resources for a storage system
#13DISTRIBUTED PROTOCOL ENDPOINT SERVICES FOR DATA STORAGE SYSTEMS
#14Load balacing for distibuted computing
#15Optimized communication pathways in a vast storage system
#16Customized hash algorithms
#17Scale out storage platform having active failover
#18Configurable hyperconverged multi-tenant storage system
#19Package on package memory interface and configuration with error code correction
#20Storage system accommodating varying storage capacities
#21Rollback procedure for failed dataset image operation
#22Reconfiguration control device
#23STORAGE SYSTEM COMMUNICATION FOR DATA RESILIENCY
#24Maintaining two-site configuration for workload availability between sites at unlimited distances for products and services
#25Copying data from mirrored storage to auxiliary storage arrays co-located with primary storage arrays
#26Configurable hyperconverged multi-tenant storage system
#27Network authentication for a storage system
#28Error detection using vector processing circuitry
#29Configurable computer memory
#30Method and apparatus for redundant data processing in which there is no checking for determining whether respective transformations are linked to a correct processor core
#31Message synchronization system
#32Copying data from mirrored storage to auxiliary storage arrays co-located with primary storage arrays
#33Package on package memory interface and configuration with error code correction
#34Utilization of erasure codes in a storage system
#35Multi-core processor and operation method thereof
#36System, method and recording medium for antifragile computing problem management
#37Hyperconverged storage system with distributable processing power
#38Distributed computing of a task utilizing a copy of an original file stored on a recovery site and based on file modification times
#39Distributed computing utilizing a recovery site
#40Multiprocessor system
#41Processor system, engine control system and control method
#42Creating and verifying successful creation of a dataset image of a dataset stored across a plurality of storage systems
#43System, method and recording medium for antifragile computing problem management
#44Regaining redundancy in distributed raid arrays using unallocated capacity
#45Efficient mechanism to replicate data for multiple controllers
#46Systems and methods for overlapping parity sectors
#47AVOIDING ENCRYPTION IN A DEDUPLICATION STORAGE
#48Method and apparatus for managing data recovery of distributed storage system
#49Systems and methods for pre-generation and pre-storage of repair fragments in storage systems
#50Multi stream deduplicated backup of collaboration server data
#51Maintaining two-site configuration for workload availability between sites at unlimited distances for products and services
#52Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting
#53Management system of server system including a plurality of servers
#54Multi-channel network-on-a-chip
#55Storage cluster
#56Faulty core recovery mechanisms for a three-dimensional network on a processor array
#57Maintaining two-site configuration for workload availability between sites at unlimited distances for products and services
#58Avoiding encryption in a deduplication storage
#59Avoiding encryption of certain blocks in a deduplication vault
#60Storage cluster
#61Processor system, engine control system and control method
#62Interface for interchanging data between redundant programs for controlling a motor vehicle
#63Detecting success or failure to create storage object images
#64Systems and methods for a mass data storage system having a file-based interface to a host and a non-file-based interface to secondary storage
#65Systems and methods for a mass data storage system having a file-based interface to a host and a non-file-based interface to secondary storage
#66Storage cluster
#67Systems and methods for extended power performance capability discovery for a modular chassis
#68Redundancy processing method and system, and information processing apparatus thereof
#69Method for controlling process based on network operation mode and apparatus therefor
#70Package on package memory interface and configuration with error code correction
#71Storage system and method of controlling storage system
#72Configurable computer memory
#73HIGH AVAILABILITY SYSTEM, REPLICATOR AND METHOD
#74Maintaining two-site configuration for workload availability between sites at unlimited distances for products and services
#75Method and apparatus for reducing read latency
#76Information processing system and control method thereof
#77Redundant execution for reliability in a super FMA ALU
#78System and method for extending system uptime while running on backup power
#79Semiconductor integrated circuit and method for operating same
#80Redundant control device and network system
#81Multi-core microcontroller having comparator for checking processing results
#82Shared ethernet adapter (SEA) load sharing and SEA fail-over configuration as set by a user interface
#83Redundant Transactional Memory
#84Fault tolerance of data processing steps operating in either a parallel operation mode or a non-synchronous redundant operation mode
#85Cache memory with dynamic lockstep support
#86Dynamic lockstep cache memory replacement logic
#87Multiprocessor switch with selective pairing
#88Scheduler for multiprocessor system switch with selective pairing
#89State recovery and lockstep execution restart in a system with multiprocessor pairing
#90System and method for extending system uptime while running on backup power
#91Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting
#92PROCESSOR AND IMAGE PROCESSING SYSTEM USING THE SAME
#93Fault tolerant stability critical execution checking using redundant execution pipelines
#94Computer system including an interrupt controller
#95MULTICHANNEL CONTROLLER MODULE
#96TASK MANAGEMENT CONTROL APPARATUS AND METHOD HAVING REDUNDANT PROCESSING COMPARISON
#97Storage apparatus and storage system
#98System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic
#99Data processing system, data processing method, and apparatus
#100Processor based system having ECC based check and access validation information means
#101Method For Changing Over A System Having Multiple Execution Units
#102Reliable execution using compare and transfer instruction on an SMT machine
#103METHOD AND DEVICE FOR CONTROLLING A COMPUTER SYSTEM HAVING AT LEAST TWO GROUPS OF INTERNAL STATES
#104Processor system and operation mode switching method for processor system
#105METHOD AND A DEVICE FOR CONTROLLING A MEMORY ACCESS IN A COMPUTER SYSTEM HAVING AT LEAST TWO EXECUTION UNITS
#106Method and device for monitoring functions of a computer system
#107Electronic system for detecting a fault
#108Multi-core microcontroller having comparator for checking processing result
#109System with configurable functional units and method
#110METHOD AND DEVICE FOR ESTABLISHING AN INITIAL STATE FOR A COMPUTER SYSTEM HAVING AT LEAST TWO EXECUTION UNITS BY MARKING REGISTERS
#111Device and Method for Storing Data and/or Instructions in a Computer System Having At Least Two Processing Units and At Least One First Memory or Memory Area for Data and/or Instructions
#112Method and Device for Controlling a Computer System
#113Method and Device for Data Processing
#114Method and device for performing switchover operations in a computer system having at least two execution units
#115HIGH-INTEGRITY COMPUTATION ARCHITECTURE WITH MULTIPLE SUPERVISED RESOURCES
#116Method and system for generating a valid signal
#117Method and device for synchronizing in a multiprocessor system
#118METHOD AND ON-CHIP CONTROL APPARATUS FOR ENHANCING PROCESS RELIABILITY AND PROCESS VARIABILITY THROUGH 3D INTEGRATION
#119Method and device for controlling a computer system
#120Device and method for performing switchover operations in a computer system having at least two execution units
#121Method and device for a switchover and for a data comparison in a computer system having at least two processing units
#122Method and device for generating a signal in a computer system having a plurality of components
#123Method and Device for Processing Data Words and/or Instructions
#124Method for high integrity and high availability computer processing
#125Method for error registration and corresponding register
#126Method and Device for Performing Switchover Operations and for Comparing Data in a Computer System Having at Least Three Execution Units
#127Method and Device for Performing Switchover Operations in a Computer System Having at Least Two Processing Units
#128Method and Device for Switching Over in a Computer System Having at Least Two Execution Units
#129Method and Device for Switching Over Between Operating Modes of a Multi-Processor System Using at Least One External Signal
#130Method and Device for Performing Switchover Operations and for Comparing Signals in a Computer System Having at Least Two Processing Units
#131Method and device for switching over in a computer system having at least two execution units
#132Method and Device for Analyzing a Signal from a Computer System Having at Least Two Execution Units
#133Method and device for clock changeover in a multi-processor system
#134Method and Device for Performing Switchover Operations and for Signal Comparison in a Computer System Having at Least Two Processing Units
#135Method for Data Distribution and Data Distribution Unit in a Multiprocessor System
#136Method And Device For Monitoring A Memory Unit In A Mutliprocessor System
#137Method And Device For Operand Processing In A Processing Unit
#138Method and Device for Delaying Access to Data and/or Instructions of a Multiprocessor System
#139Method for Delaying Accesses to Date and/or Instructions of a Two-Computer System, and Corresponding Delay Unit
#140Method For Switching Over Between At Least Two Operating Modes Of A Processor Unit, As Well Corresponding Processor Unit
#141Method and Device for Switching Over in a Computer System Having at Least Two Execution Units
#142Method and Device for Switching Between at Least Two Operating Modes of a Processor Unit
#143Hardware configurable CPU with high availability mode
#144Systems and methods for a mass data storage system having a file-based interface to a host and a non-file-based interface to secondary storage
#145Task management control apparatus and method, having redundant processing comparison
#146Method and apparatus for recovery from loss of lock step
#147Computing with both lock-step and free-step processor modes
#148System and method for dynamically optimizing performance and reliability of redundant processing systems
#149Lockstep error signaling
#150Off-chip lockstep checking
#151Architectural support for selective use of high-reliability mode in a computer system
#152Efficient load balancing
#153Multi-chassis array with multi-level load balancing
#154System and method of dynamic system resource allocation for primary storage systems with virtualized embedded data protection
#155Method and system for checkerboard RAID
#156Avoiding encryption of certain blocks in a deduplication vault
#157Systems and methods for improved data management in data storage systems