Inter-processor communication method for access latency between system-in-package (SIP) dies

System and method for dynamic buffer sizing in a computing device

FIFO memory having a memory region modifiable during operation

Method and system for queuing data for multiple readers and writers

Resizable and relocatable queue

Virtual load store queue having a dynamic dispatch window with a distributed structure

Virtual load store queue having a dynamic dispatch window with a unified structure

Multiple, per sensor configurable FIFOs in a single static random access memory (SRAM) structure

Dynamically resizable circular buffers

Method for extracting IBIS simulation model

Buffering of a data stream

Green mode data buffer control

Efficient buffer utilization in a computer network-based messaging system

Size and retry programmable multi-synchronous FIFO

BUFFER CONTROL METHOD AND STORAGE APPARATUS

Buffer circuit and buffer control method

Adjustable elasticity FIFO buffer with preload value having a number of storage cells equal to frequency offset times between data units in a data stream

FIFO-type one-way interfacing device between a master unit and a slave unit, and corresponding master unit and slave unit

Configurable length first-in first-out memory

Compact and hitlessly-resizable multi-channel queue

Dynamic memory buffer

Full/selector output from one of plural flag generation count outputs

Dynamic FIFO for simulation

Adjustable elasticity FIFO buffer have a number of storage cells equal to a frequency offset times a number of data units in a data stream

Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation